1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <mpc83xx.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Breathe some life into the CPU... 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * Set up the memory map, 16*4882a593Smuzhiyun * initialize a bunch of registers, 17*4882a593Smuzhiyun * initialize the UPM's 18*4882a593Smuzhiyun */ cpu_init_f(volatile immap_t * im)19*4882a593Smuzhiyunvoid cpu_init_f (volatile immap_t * im) 20*4882a593Smuzhiyun { 21*4882a593Smuzhiyun /* Pointer is writable since we allocated a register for it */ 22*4882a593Smuzhiyun gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* global data region was cleared in start.S */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* system performance tweaking */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #ifdef CONFIG_SYS_ACR_PIPE_DEP 29*4882a593Smuzhiyun /* Arbiter pipeline depth */ 30*4882a593Smuzhiyun im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | 31*4882a593Smuzhiyun (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); 32*4882a593Smuzhiyun #endif 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #ifdef CONFIG_SYS_ACR_RPTCNT 35*4882a593Smuzhiyun /* Arbiter repeat count */ 36*4882a593Smuzhiyun im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | 37*4882a593Smuzhiyun (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); 38*4882a593Smuzhiyun #endif 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #ifdef CONFIG_SYS_SPCR_OPT 41*4882a593Smuzhiyun /* Optimize transactions between CSB and other devices */ 42*4882a593Smuzhiyun im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | 43*4882a593Smuzhiyun (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); 44*4882a593Smuzhiyun #endif 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Enable Time Base & Decrementer (so we will have udelay()) */ 47*4882a593Smuzhiyun im->sysconf.spcr |= SPCR_TBEN; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* DDR control driver register */ 50*4882a593Smuzhiyun #ifdef CONFIG_SYS_DDRCDR 51*4882a593Smuzhiyun im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun /* Output buffer impedance register */ 54*4882a593Smuzhiyun #ifdef CONFIG_SYS_OBIR 55*4882a593Smuzhiyun im->sysconf.obir = CONFIG_SYS_OBIR; 56*4882a593Smuzhiyun #endif 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * Memory Controller: 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary 63*4882a593Smuzhiyun * addresses - these have to be modified later when FLASH size 64*4882a593Smuzhiyun * has been determined 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #if defined(CONFIG_SYS_NAND_BR_PRELIM) \ 68*4882a593Smuzhiyun && defined(CONFIG_SYS_NAND_OR_PRELIM) \ 69*4882a593Smuzhiyun && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ 70*4882a593Smuzhiyun && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) 71*4882a593Smuzhiyun set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); 72*4882a593Smuzhiyun set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); 73*4882a593Smuzhiyun im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; 74*4882a593Smuzhiyun im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; 75*4882a593Smuzhiyun #else 76*4882a593Smuzhiyun #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined 77*4882a593Smuzhiyun #endif 78*4882a593Smuzhiyun } 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* 81*4882a593Smuzhiyun * Get timebase clock frequency (like cpu_clk in Hz) 82*4882a593Smuzhiyun */ get_tbclk(void)83*4882a593Smuzhiyununsigned long get_tbclk(void) 84*4882a593Smuzhiyun { 85*4882a593Smuzhiyun return (gd->bus_clk + 3L) / 4L; 86*4882a593Smuzhiyun } 87*4882a593Smuzhiyun puts(const char * str)88*4882a593Smuzhiyunvoid puts(const char *str) 89*4882a593Smuzhiyun { 90*4882a593Smuzhiyun while (*str) 91*4882a593Smuzhiyun putc(*str++); 92*4882a593Smuzhiyun } 93