1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
3*4882a593Smuzhiyun * Copyright (C) 2009, Wind River Systems Inc
4*4882a593Smuzhiyun * Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/cache.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
13*4882a593Smuzhiyun
__flush_dcache(unsigned long start,unsigned long end)14*4882a593Smuzhiyun static void __flush_dcache(unsigned long start, unsigned long end)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun unsigned long addr;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun start &= ~(gd->arch.dcache_line_size - 1);
19*4882a593Smuzhiyun end += (gd->arch.dcache_line_size - 1);
20*4882a593Smuzhiyun end &= ~(gd->arch.dcache_line_size - 1);
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun for (addr = start; addr < end; addr += gd->arch.dcache_line_size) {
23*4882a593Smuzhiyun __asm__ __volatile__ (" flushda 0(%0)\n"
24*4882a593Smuzhiyun : /* Outputs */
25*4882a593Smuzhiyun : /* Inputs */ "r"(addr)
26*4882a593Smuzhiyun /* : No clobber */);
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
__flush_dcache_all(unsigned long start,unsigned long end)30*4882a593Smuzhiyun static void __flush_dcache_all(unsigned long start, unsigned long end)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun unsigned long addr;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun start &= ~(gd->arch.dcache_line_size - 1);
35*4882a593Smuzhiyun end += (gd->arch.dcache_line_size - 1);
36*4882a593Smuzhiyun end &= ~(gd->arch.dcache_line_size - 1);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun if (end > start + gd->arch.dcache_size)
39*4882a593Smuzhiyun end = start + gd->arch.dcache_size;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun for (addr = start; addr < end; addr += gd->arch.dcache_line_size) {
42*4882a593Smuzhiyun __asm__ __volatile__ (" flushd 0(%0)\n"
43*4882a593Smuzhiyun : /* Outputs */
44*4882a593Smuzhiyun : /* Inputs */ "r"(addr)
45*4882a593Smuzhiyun /* : No clobber */);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
__invalidate_dcache(unsigned long start,unsigned long end)49*4882a593Smuzhiyun static void __invalidate_dcache(unsigned long start, unsigned long end)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun unsigned long addr;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun start &= ~(gd->arch.dcache_line_size - 1);
54*4882a593Smuzhiyun end += (gd->arch.dcache_line_size - 1);
55*4882a593Smuzhiyun end &= ~(gd->arch.dcache_line_size - 1);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun for (addr = start; addr < end; addr += gd->arch.dcache_line_size) {
58*4882a593Smuzhiyun __asm__ __volatile__ (" initda 0(%0)\n"
59*4882a593Smuzhiyun : /* Outputs */
60*4882a593Smuzhiyun : /* Inputs */ "r"(addr)
61*4882a593Smuzhiyun /* : No clobber */);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
__flush_icache(unsigned long start,unsigned long end)65*4882a593Smuzhiyun static void __flush_icache(unsigned long start, unsigned long end)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun unsigned long addr;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun start &= ~(gd->arch.icache_line_size - 1);
70*4882a593Smuzhiyun end += (gd->arch.icache_line_size - 1);
71*4882a593Smuzhiyun end &= ~(gd->arch.icache_line_size - 1);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (end > start + gd->arch.icache_size)
74*4882a593Smuzhiyun end = start + gd->arch.icache_size;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun for (addr = start; addr < end; addr += gd->arch.icache_line_size) {
77*4882a593Smuzhiyun __asm__ __volatile__ (" flushi %0\n"
78*4882a593Smuzhiyun : /* Outputs */
79*4882a593Smuzhiyun : /* Inputs */ "r"(addr)
80*4882a593Smuzhiyun /* : No clobber */);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun __asm__ __volatile(" flushp\n");
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
flush_dcache_all(void)85*4882a593Smuzhiyun void flush_dcache_all(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun __flush_dcache_all(0, gd->arch.dcache_size);
88*4882a593Smuzhiyun __flush_icache(0, gd->arch.icache_size);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
flush_dcache_range(unsigned long start,unsigned long end)91*4882a593Smuzhiyun void flush_dcache_range(unsigned long start, unsigned long end)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun if (gd->arch.has_initda)
94*4882a593Smuzhiyun __flush_dcache(start, end);
95*4882a593Smuzhiyun else
96*4882a593Smuzhiyun __flush_dcache_all(start, end);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
flush_cache(unsigned long start,unsigned long size)99*4882a593Smuzhiyun void flush_cache(unsigned long start, unsigned long size)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun if (gd->arch.has_initda)
102*4882a593Smuzhiyun __flush_dcache(start, start + size);
103*4882a593Smuzhiyun else
104*4882a593Smuzhiyun __flush_dcache_all(start, start + size);
105*4882a593Smuzhiyun __flush_icache(start, start + size);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
invalidate_dcache_range(unsigned long start,unsigned long end)108*4882a593Smuzhiyun void invalidate_dcache_range(unsigned long start, unsigned long end)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun if (gd->arch.has_initda)
111*4882a593Smuzhiyun __invalidate_dcache(start, end);
112*4882a593Smuzhiyun else
113*4882a593Smuzhiyun __flush_dcache_all(start, end);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
dcache_status(void)116*4882a593Smuzhiyun int dcache_status(void)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun return 1;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
dcache_enable(void)121*4882a593Smuzhiyun void dcache_enable(void)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun flush_dcache_all();
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
dcache_disable(void)126*4882a593Smuzhiyun void dcache_disable(void)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun flush_dcache_all();
129*4882a593Smuzhiyun }
130