1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 3*4882a593Smuzhiyun * Scott McNutt <smcnutt@psyent.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_NIOS2_H__ 9*4882a593Smuzhiyun #define __ASM_NIOS2_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /*------------------------------------------------------------------------ 12*4882a593Smuzhiyun * Control registers -- use with wrctl() & rdctl() 13*4882a593Smuzhiyun *----------------------------------------------------------------------*/ 14*4882a593Smuzhiyun #define CTL_STATUS 0 /* Processor status reg */ 15*4882a593Smuzhiyun #define CTL_ESTATUS 1 /* Exception status reg */ 16*4882a593Smuzhiyun #define CTL_BSTATUS 2 /* Break status reg */ 17*4882a593Smuzhiyun #define CTL_IENABLE 3 /* Interrut enable reg */ 18*4882a593Smuzhiyun #define CTL_IPENDING 4 /* Interrut pending reg */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /*------------------------------------------------------------------------ 21*4882a593Smuzhiyun * Access to control regs 22*4882a593Smuzhiyun *----------------------------------------------------------------------*/ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define rdctl(reg) __builtin_rdctl(reg) 25*4882a593Smuzhiyun #define wrctl(reg, val) __builtin_wrctl(reg, val) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /*------------------------------------------------------------------------ 28*4882a593Smuzhiyun * Control reg bit masks 29*4882a593Smuzhiyun *----------------------------------------------------------------------*/ 30*4882a593Smuzhiyun #define STATUS_IE (1<<0) /* Interrupt enable */ 31*4882a593Smuzhiyun #define STATUS_U (1<<1) /* User-mode */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /*------------------------------------------------------------------------ 34*4882a593Smuzhiyun * Bit-31 Cache bypass -- only valid for data access. When data cache 35*4882a593Smuzhiyun * is not implemented, bit 31 is ignored for compatibility. 36*4882a593Smuzhiyun *----------------------------------------------------------------------*/ 37*4882a593Smuzhiyun #define CACHE_BYPASS(a) ((a) | 0x80000000) 38*4882a593Smuzhiyun #define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* __ASM_NIOS2_H__ */ 41