1*4882a593Smuzhiyun #ifndef __ASM_NIOS2_DMA_MAPPING_H 2*4882a593Smuzhiyun #define __ASM_NIOS2_DMA_MAPPING_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #include <memalign.h> 5*4882a593Smuzhiyun #include <asm/io.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * dma_alloc_coherent() return cache-line aligned allocation which is mapped 9*4882a593Smuzhiyun * to uncached io region. 10*4882a593Smuzhiyun */ dma_alloc_coherent(size_t len,unsigned long * handle)11*4882a593Smuzhiyunstatic inline void *dma_alloc_coherent(size_t len, unsigned long *handle) 12*4882a593Smuzhiyun { 13*4882a593Smuzhiyun unsigned long addr = (unsigned long)malloc_cache_aligned(len); 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun if (!addr) 16*4882a593Smuzhiyun return NULL; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun invalidate_dcache_range(addr, addr + len); 19*4882a593Smuzhiyun if (handle) 20*4882a593Smuzhiyun *handle = addr; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun return map_physmem(addr, len, MAP_NOCACHE); 23*4882a593Smuzhiyun } 24*4882a593Smuzhiyun #endif /* __ASM_NIOS2_DMA_MAPPING_H */ 25