1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 3*4882a593Smuzhiyun * Scott McNutt <smcnutt@psyent.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_NIOS2_CACHE_H_ 9*4882a593Smuzhiyun #define __ASM_NIOS2_CACHE_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 13*4882a593Smuzhiyun * 16, and 32 bytes. We default to the largest of these values for 14*4882a593Smuzhiyun * alignment of DMA buffers. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN 32 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #endif /* __ASM_NIOS2_CACHE_H_ */ 19