xref: /OK3568_Linux_fs/u-boot/arch/nios2/dts/3c120_devboard.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun *  Copyright (C) 2013 Altera Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is generated by sopc2dts.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier:	GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/dts-v1/;
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "altr,qsys_ghrd_3c120";
13*4882a593Smuzhiyun	compatible = "altr,qsys_ghrd_3c120";
14*4882a593Smuzhiyun	#address-cells = <1>;
15*4882a593Smuzhiyun	#size-cells = <1>;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	cpus {
18*4882a593Smuzhiyun		#address-cells = <1>;
19*4882a593Smuzhiyun		#size-cells = <0>;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		cpu: cpu@0x0 {
22*4882a593Smuzhiyun			device_type = "cpu";
23*4882a593Smuzhiyun			compatible = "altr,nios2-1.0";
24*4882a593Smuzhiyun			reg = <0x00000000>;
25*4882a593Smuzhiyun			interrupt-controller;
26*4882a593Smuzhiyun			#interrupt-cells = <1>;
27*4882a593Smuzhiyun			clock-frequency = <125000000>;
28*4882a593Smuzhiyun			dcache-line-size = <32>;
29*4882a593Smuzhiyun			icache-line-size = <32>;
30*4882a593Smuzhiyun			dcache-size = <32768>;
31*4882a593Smuzhiyun			icache-size = <32768>;
32*4882a593Smuzhiyun			altr,implementation = "fast";
33*4882a593Smuzhiyun			altr,pid-num-bits = <8>;
34*4882a593Smuzhiyun			altr,tlb-num-ways = <16>;
35*4882a593Smuzhiyun			altr,tlb-num-entries = <128>;
36*4882a593Smuzhiyun			altr,tlb-ptr-sz = <7>;
37*4882a593Smuzhiyun			altr,has-div = <1>;
38*4882a593Smuzhiyun			altr,has-mul = <1>;
39*4882a593Smuzhiyun			altr,reset-addr = <0xc2800000>;
40*4882a593Smuzhiyun			altr,fast-tlb-miss-addr = <0xc7fff400>;
41*4882a593Smuzhiyun			altr,exception-addr = <0xd0000020>;
42*4882a593Smuzhiyun			altr,has-initda = <1>;
43*4882a593Smuzhiyun			altr,has-mmu = <1>;
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	memory@0 {
48*4882a593Smuzhiyun		device_type = "memory";
49*4882a593Smuzhiyun		reg = <0x10000000 0x08000000>,
50*4882a593Smuzhiyun			<0x07fff400 0x00000400>;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	sopc@0 {
54*4882a593Smuzhiyun		device_type = "soc";
55*4882a593Smuzhiyun		ranges;
56*4882a593Smuzhiyun		#address-cells = <1>;
57*4882a593Smuzhiyun		#size-cells = <1>;
58*4882a593Smuzhiyun		compatible = "altr,avalon", "simple-bus";
59*4882a593Smuzhiyun		bus-frequency = <125000000>;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun		pb_cpu_to_io: bridge@0x8000000 {
62*4882a593Smuzhiyun			compatible = "simple-bus";
63*4882a593Smuzhiyun			reg = <0x08000000 0x00800000>;
64*4882a593Smuzhiyun			#address-cells = <1>;
65*4882a593Smuzhiyun			#size-cells = <1>;
66*4882a593Smuzhiyun			ranges = <0x00002000 0x08002000 0x00002000>,
67*4882a593Smuzhiyun				<0x00004000 0x08004000 0x00000400>,
68*4882a593Smuzhiyun				<0x00004400 0x08004400 0x00000040>,
69*4882a593Smuzhiyun				<0x00004800 0x08004800 0x00000040>,
70*4882a593Smuzhiyun				<0x00004c80 0x08004c80 0x00000020>,
71*4882a593Smuzhiyun				<0x00004cc0 0x08004cc0 0x00000010>,
72*4882a593Smuzhiyun				<0x00004ce0 0x08004ce0 0x00000010>,
73*4882a593Smuzhiyun				<0x00004d00 0x08004d00 0x00000010>,
74*4882a593Smuzhiyun				<0x00004d40 0x08004d40 0x00000008>,
75*4882a593Smuzhiyun				<0x00004d50 0x08004d50 0x00000008>,
76*4882a593Smuzhiyun				<0x00008000 0x08008000 0x00000020>,
77*4882a593Smuzhiyun				<0x00400000 0x08400000 0x00000020>;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun			timer_1ms: timer@0x400000 {
80*4882a593Smuzhiyun				compatible = "altr,timer-1.0";
81*4882a593Smuzhiyun				reg = <0x00400000 0x00000020>;
82*4882a593Smuzhiyun				interrupt-parent = <&cpu>;
83*4882a593Smuzhiyun				interrupts = <11>;
84*4882a593Smuzhiyun				clock-frequency = <125000000>;
85*4882a593Smuzhiyun			};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun			timer_0: timer@0x8000 {
88*4882a593Smuzhiyun				compatible = "altr,timer-1.0";
89*4882a593Smuzhiyun				reg = < 0x00008000 0x00000020 >;
90*4882a593Smuzhiyun				interrupt-parent = < &cpu >;
91*4882a593Smuzhiyun				interrupts = < 5 >;
92*4882a593Smuzhiyun				clock-frequency = < 125000000 >;
93*4882a593Smuzhiyun			};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun			sysid: sysid@0x4d40 {
96*4882a593Smuzhiyun				compatible = "altr,sysid-1.0";
97*4882a593Smuzhiyun				reg = <0x00004d40 0x00000008>;
98*4882a593Smuzhiyun			};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun			jtag_uart: serial@0x4d50 {
101*4882a593Smuzhiyun				compatible = "altr,juart-1.0";
102*4882a593Smuzhiyun				reg = <0x00004d50 0x00000008>;
103*4882a593Smuzhiyun				interrupt-parent = <&cpu>;
104*4882a593Smuzhiyun				interrupts = <1>;
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun			tse_mac: ethernet@0x4000 {
108*4882a593Smuzhiyun				compatible = "altr,tse-1.0";
109*4882a593Smuzhiyun				reg = <0x00004000 0x00000400>,
110*4882a593Smuzhiyun					<0x00004400 0x00000040>,
111*4882a593Smuzhiyun					<0x00004800 0x00000040>,
112*4882a593Smuzhiyun					<0x00002000 0x00002000>;
113*4882a593Smuzhiyun				reg-names = "control_port", "rx_csr", "tx_csr", "s1";
114*4882a593Smuzhiyun				interrupt-parent = <&cpu>;
115*4882a593Smuzhiyun				interrupts = <2 3>;
116*4882a593Smuzhiyun				interrupt-names = "rx_irq", "tx_irq";
117*4882a593Smuzhiyun				rx-fifo-depth = <8192>;
118*4882a593Smuzhiyun				tx-fifo-depth = <8192>;
119*4882a593Smuzhiyun				max-frame-size = <1518>;
120*4882a593Smuzhiyun				local-mac-address = [ 00 00 00 00 00 00 ];
121*4882a593Smuzhiyun				phy-mode = "rgmii-id";
122*4882a593Smuzhiyun				phy-handle = <&phy0>;
123*4882a593Smuzhiyun				tse_mac_mdio: mdio {
124*4882a593Smuzhiyun					compatible = "altr,tse-mdio";
125*4882a593Smuzhiyun					#address-cells = <1>;
126*4882a593Smuzhiyun					#size-cells = <0>;
127*4882a593Smuzhiyun					phy0: ethernet-phy@18 {
128*4882a593Smuzhiyun						reg = <18>;
129*4882a593Smuzhiyun						device_type = "ethernet-phy";
130*4882a593Smuzhiyun					};
131*4882a593Smuzhiyun				};
132*4882a593Smuzhiyun			};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun			uart: serial@0x4c80 {
135*4882a593Smuzhiyun				compatible = "altr,uart-1.0";
136*4882a593Smuzhiyun				reg = <0x00004c80 0x00000020>;
137*4882a593Smuzhiyun				interrupt-parent = <&cpu>;
138*4882a593Smuzhiyun				interrupts = <10>;
139*4882a593Smuzhiyun				current-speed = <115200>;
140*4882a593Smuzhiyun				clock-frequency = <62500000>;
141*4882a593Smuzhiyun			};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun			user_led_pio_8out: gpio@0x4cc0 {
144*4882a593Smuzhiyun				compatible = "altr,pio-1.0";
145*4882a593Smuzhiyun				reg = <0x00004cc0 0x00000010>;
146*4882a593Smuzhiyun				resetvalue = <255>;
147*4882a593Smuzhiyun				altr,gpio-bank-width = <8>;
148*4882a593Smuzhiyun				#gpio-cells = <2>;
149*4882a593Smuzhiyun				gpio-controller;
150*4882a593Smuzhiyun				gpio-bank-name = "led";
151*4882a593Smuzhiyun			};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun			user_dipsw_pio_8in: gpio@0x4ce0 {
154*4882a593Smuzhiyun				compatible = "altr,pio-1.0";
155*4882a593Smuzhiyun				reg = <0x00004ce0 0x00000010>;
156*4882a593Smuzhiyun				interrupt-parent = <&cpu>;
157*4882a593Smuzhiyun				interrupts = <8>;
158*4882a593Smuzhiyun				edge_type = <2>;
159*4882a593Smuzhiyun				level_trigger = <0>;
160*4882a593Smuzhiyun				resetvalue = <0>;
161*4882a593Smuzhiyun				altr,gpio-bank-width = <8>;
162*4882a593Smuzhiyun				#gpio-cells = <2>;
163*4882a593Smuzhiyun				gpio-controller;
164*4882a593Smuzhiyun				gpio-bank-name = "dipsw";
165*4882a593Smuzhiyun			};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun			user_pb_pio_4in: gpio@0x4d00 {
168*4882a593Smuzhiyun				compatible = "altr,pio-1.0";
169*4882a593Smuzhiyun				reg = <0x00004d00 0x00000010>;
170*4882a593Smuzhiyun				interrupt-parent = <&cpu>;
171*4882a593Smuzhiyun				interrupts = <9>;
172*4882a593Smuzhiyun				edge_type = <2>;
173*4882a593Smuzhiyun				level_trigger = <0>;
174*4882a593Smuzhiyun				resetvalue = <0>;
175*4882a593Smuzhiyun				altr,gpio-bank-width = <4>;
176*4882a593Smuzhiyun				#gpio-cells = <2>;
177*4882a593Smuzhiyun				gpio-controller;
178*4882a593Smuzhiyun				gpio-bank-name = "pb";
179*4882a593Smuzhiyun			};
180*4882a593Smuzhiyun		};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun		cfi_flash_64m: flash@0x0 {
183*4882a593Smuzhiyun			compatible = "cfi-flash";
184*4882a593Smuzhiyun			reg = <0x00000000 0x04000000>;
185*4882a593Smuzhiyun			bank-width = <2>;
186*4882a593Smuzhiyun			device-width = <1>;
187*4882a593Smuzhiyun			#address-cells = <1>;
188*4882a593Smuzhiyun			#size-cells = <1>;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun			partition@800000 {
191*4882a593Smuzhiyun				reg = <0x00800000 0x01e00000>;
192*4882a593Smuzhiyun				label = "JFFS2 Filesystem";
193*4882a593Smuzhiyun			};
194*4882a593Smuzhiyun		};
195*4882a593Smuzhiyun	};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun	chosen {
198*4882a593Smuzhiyun		bootargs = "debug console=ttyJ0,115200";
199*4882a593Smuzhiyun		stdout-path = &jtag_uart;
200*4882a593Smuzhiyun	};
201*4882a593Smuzhiyun};
202