1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Generate definitions needed by assembly language modules.
5*4882a593Smuzhiyun * This code generates raw asm output which is post-processed to extract
6*4882a593Smuzhiyun * and format the required data.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
9*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
10*4882a593Smuzhiyun * published by the Free Software Foundation.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/kbuild.h>
15*4882a593Smuzhiyun
main(void)16*4882a593Smuzhiyun int main(void)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * TODO : Check if each entry in this file is really necessary.
20*4882a593Smuzhiyun * - struct ftahbc02s
21*4882a593Smuzhiyun * - struct ftsdmc021
22*4882a593Smuzhiyun * - struct andes_pcu
23*4882a593Smuzhiyun * - struct dwcddr21mctl
24*4882a593Smuzhiyun * are used only for generating asm-offsets.h.
25*4882a593Smuzhiyun * It means their offset addresses are referenced only from assembly
26*4882a593Smuzhiyun * code. Is it better to define the macros directly in headers?
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #ifdef CONFIG_FTSMC020
30*4882a593Smuzhiyun OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
31*4882a593Smuzhiyun OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun BLANK();
34*4882a593Smuzhiyun #ifdef CONFIG_FTAHBC020S
35*4882a593Smuzhiyun OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]);
36*4882a593Smuzhiyun OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
37*4882a593Smuzhiyun OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
38*4882a593Smuzhiyun #endif
39*4882a593Smuzhiyun BLANK();
40*4882a593Smuzhiyun #ifdef CONFIG_FTPMU010
41*4882a593Smuzhiyun OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0);
42*4882a593Smuzhiyun #endif
43*4882a593Smuzhiyun BLANK();
44*4882a593Smuzhiyun #ifdef CONFIG_FTSDMC021
45*4882a593Smuzhiyun OFFSET(FTSDMC021_TP1, ftsdmc021, tp1);
46*4882a593Smuzhiyun OFFSET(FTSDMC021_TP2, ftsdmc021, tp2);
47*4882a593Smuzhiyun OFFSET(FTSDMC021_CR1, ftsdmc021, cr1);
48*4882a593Smuzhiyun OFFSET(FTSDMC021_CR2, ftsdmc021, cr2);
49*4882a593Smuzhiyun OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr);
50*4882a593Smuzhiyun OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr);
51*4882a593Smuzhiyun OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr);
52*4882a593Smuzhiyun OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr);
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun BLANK();
55*4882a593Smuzhiyun #ifdef CONFIG_ANDES_PCU
56*4882a593Smuzhiyun OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun BLANK();
59*4882a593Smuzhiyun #ifdef CONFIG_DWCDDR21MCTL
60*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */
61*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */
62*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */
63*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */
64*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */
65*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
66*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
67*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
68*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
69*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
70*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
71*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
72*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
73*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
74*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
75*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
76*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
77*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */
78*4882a593Smuzhiyun OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
79*4882a593Smuzhiyun #endif
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83