1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Andes Technology Corporation 3*4882a593Smuzhiyun * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) 4*4882a593Smuzhiyun * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 7*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 8*4882a593Smuzhiyun * published by the Free Software Foundation. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef __ASM_NDS_PTRACE_H 11*4882a593Smuzhiyun #define __ASM_NDS_PTRACE_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define USR_MODE 0x00 14*4882a593Smuzhiyun #define SU_MODE 0x01 15*4882a593Smuzhiyun #define HV_MODE 0x10 16*4882a593Smuzhiyun #define MODE_MASK (0x03<<3) 17*4882a593Smuzhiyun #define GIE_BIT 0x01 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* this struct defines the way the registers are stored on the 22*4882a593Smuzhiyun stack during a system call. */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define NDS32_REG long 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct pt_regs { 27*4882a593Smuzhiyun NDS32_REG ir0; 28*4882a593Smuzhiyun NDS32_REG ipsw; 29*4882a593Smuzhiyun NDS32_REG ipc; 30*4882a593Smuzhiyun NDS32_REG sp; 31*4882a593Smuzhiyun NDS32_REG orig_r0; 32*4882a593Smuzhiyun NDS32_REG pipsw; 33*4882a593Smuzhiyun NDS32_REG pipc; 34*4882a593Smuzhiyun NDS32_REG pp0; 35*4882a593Smuzhiyun NDS32_REG pp1; 36*4882a593Smuzhiyun NDS32_REG d0hi; 37*4882a593Smuzhiyun NDS32_REG d0lo; 38*4882a593Smuzhiyun NDS32_REG d1hi; 39*4882a593Smuzhiyun NDS32_REG d1lo; 40*4882a593Smuzhiyun NDS32_REG r[26]; /* r0 - r25 */ 41*4882a593Smuzhiyun NDS32_REG p0; /* r26 - used by OS */ 42*4882a593Smuzhiyun NDS32_REG p1; /* r27 - used by OS */ 43*4882a593Smuzhiyun NDS32_REG fp; /* r28 */ 44*4882a593Smuzhiyun NDS32_REG gp; /* r29 */ 45*4882a593Smuzhiyun NDS32_REG lp; /* r30 */ 46*4882a593Smuzhiyun NDS32_REG fucop_ctl; 47*4882a593Smuzhiyun NDS32_REG osp; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define processor_mode(regs) \ 51*4882a593Smuzhiyun (((regs)->ipsw & MODE_MASK) >> 3) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define interrupts_enabled(regs) \ 54*4882a593Smuzhiyun ((regs)->ipsw & GIE_BIT) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * Offsets used by 'ptrace' system call interface. 58*4882a593Smuzhiyun * These can't be changed without breaking binary compatibility 59*4882a593Smuzhiyun * with MkLinux, etc. 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #define PT_R0 0 62*4882a593Smuzhiyun #define PT_R1 1 63*4882a593Smuzhiyun #define PT_R2 2 64*4882a593Smuzhiyun #define PT_R3 3 65*4882a593Smuzhiyun #define PT_R4 4 66*4882a593Smuzhiyun #define PT_R5 5 67*4882a593Smuzhiyun #define PT_R6 6 68*4882a593Smuzhiyun #define PT_R7 7 69*4882a593Smuzhiyun #define PT_R8 8 70*4882a593Smuzhiyun #define PT_R9 9 71*4882a593Smuzhiyun #define PT_R10 10 72*4882a593Smuzhiyun #define PT_R11 11 73*4882a593Smuzhiyun #define PT_R12 12 74*4882a593Smuzhiyun #define PT_R13 13 75*4882a593Smuzhiyun #define PT_R14 14 76*4882a593Smuzhiyun #define PT_R15 15 77*4882a593Smuzhiyun #define PT_R16 16 78*4882a593Smuzhiyun #define PT_R17 17 79*4882a593Smuzhiyun #define PT_R18 18 80*4882a593Smuzhiyun #define PT_R19 19 81*4882a593Smuzhiyun #define PT_R20 20 82*4882a593Smuzhiyun #define PT_R21 21 83*4882a593Smuzhiyun #define PT_R22 22 84*4882a593Smuzhiyun #define PT_R23 23 85*4882a593Smuzhiyun #define PT_R24 24 86*4882a593Smuzhiyun #define PT_R25 25 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* __ASM_NDS_PTRACE_H */ 91