1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Andes Technology Corporation 3*4882a593Smuzhiyun * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4*4882a593Smuzhiyun * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_CACHE_H 10*4882a593Smuzhiyun #define _ASM_CACHE_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* cache */ 13*4882a593Smuzhiyun int icache_status(void); 14*4882a593Smuzhiyun void icache_enable(void); 15*4882a593Smuzhiyun void icache_disable(void); 16*4882a593Smuzhiyun int dcache_status(void); 17*4882a593Smuzhiyun void dcache_enable(void); 18*4882a593Smuzhiyun void dcache_disable(void); 19*4882a593Smuzhiyun void cache_flush(void); 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define DEFINE_GET_SYS_REG(reg) \ 22*4882a593Smuzhiyun static inline unsigned long GET_##reg(void) \ 23*4882a593Smuzhiyun { \ 24*4882a593Smuzhiyun unsigned long val; \ 25*4882a593Smuzhiyun __asm__ volatile ( \ 26*4882a593Smuzhiyun "mfsr %0, $"#reg : "=&r" (val) : : "memory" \ 27*4882a593Smuzhiyun ); \ 28*4882a593Smuzhiyun return val; \ 29*4882a593Smuzhiyun } 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum cache_t {ICACHE, DCACHE}; 32*4882a593Smuzhiyun DEFINE_GET_SYS_REG(ICM_CFG); 33*4882a593Smuzhiyun DEFINE_GET_SYS_REG(DCM_CFG); 34*4882a593Smuzhiyun /* I-cache sets (# of cache lines) per way */ 35*4882a593Smuzhiyun #define ICM_CFG_OFF_ISET 0 36*4882a593Smuzhiyun /* I-cache ways */ 37*4882a593Smuzhiyun #define ICM_CFG_OFF_IWAY 3 38*4882a593Smuzhiyun #define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET) 39*4882a593Smuzhiyun #define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY) 40*4882a593Smuzhiyun /* D-cache sets (# of cache lines) per way */ 41*4882a593Smuzhiyun #define DCM_CFG_OFF_DSET 0 42*4882a593Smuzhiyun /* D-cache ways */ 43*4882a593Smuzhiyun #define DCM_CFG_OFF_DWAY 3 44*4882a593Smuzhiyun #define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET) 45*4882a593Smuzhiyun #define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY) 46*4882a593Smuzhiyun /* I-cache line size */ 47*4882a593Smuzhiyun #define ICM_CFG_OFF_ISZ 6 48*4882a593Smuzhiyun #define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) 49*4882a593Smuzhiyun /* D-cache line size */ 50*4882a593Smuzhiyun #define DCM_CFG_OFF_DSZ 6 51*4882a593Smuzhiyun #define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. 55*4882a593Smuzhiyun * We use that value for aligning DMA buffers unless the board config has 56*4882a593Smuzhiyun * specified an alternate cache line size. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #ifdef CONFIG_SYS_CACHELINE_SIZE 59*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 60*4882a593Smuzhiyun #else 61*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN 32 62*4882a593Smuzhiyun #endif 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* _ASM_CACHE_H */ 65