1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Andes Technology Corporation 3*4882a593Smuzhiyun * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __AG102_H 9*4882a593Smuzhiyun #define __AG102_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Hardware register bases 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* PCI Controller */ 16*4882a593Smuzhiyun #define CONFIG_FTPCI100_BASE 0x90000000 17*4882a593Smuzhiyun /* LPC Controller */ 18*4882a593Smuzhiyun #define CONFIG_LPC_IO_BASE 0x90100000 19*4882a593Smuzhiyun /* LPC Controller */ 20*4882a593Smuzhiyun #define CONFIG_LPC_BASE 0x90200000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* NDS32 Data Local Memory 01 */ 23*4882a593Smuzhiyun #define CONFIG_NDS_DLM1_BASE 0x90300000 24*4882a593Smuzhiyun /* NDS32 Data Local Memory 02 */ 25*4882a593Smuzhiyun #define CONFIG_NDS_DLM2_BASE 0x90400000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Synopsys DWC DDR2/1 Controller */ 28*4882a593Smuzhiyun #define CONFIG_DWCDDR21MCTL_BASE 0x90500000 29*4882a593Smuzhiyun /* DMA Controller */ 30*4882a593Smuzhiyun #define CONFIG_FTDMAC020_BASE 0x90600000 31*4882a593Smuzhiyun /* FTIDE020_S IDE (ATA) Controller */ 32*4882a593Smuzhiyun #define CONFIG_FTIDE020S_BASE 0x90700000 33*4882a593Smuzhiyun /* USB OTG Controller */ 34*4882a593Smuzhiyun #define CONFIG_FZOTG266HD0A_BASE 0x90800000 35*4882a593Smuzhiyun /* Andes L2 Cache Controller */ 36*4882a593Smuzhiyun #define CONFIG_NCEL2C100_BASE 0x90900000 37*4882a593Smuzhiyun /* XGI XG22 GPU */ 38*4882a593Smuzhiyun #define CONFIG_XGI_XG22_BASE 0x90A00000 39*4882a593Smuzhiyun /* GMAC Ethernet Controller */ 40*4882a593Smuzhiyun #define CONFIG_FTGMAC100_BASE 0x90B00000 41*4882a593Smuzhiyun /* AHB Controller */ 42*4882a593Smuzhiyun #define CONFIG_FTAHBC020S_BASE 0x90C00000 43*4882a593Smuzhiyun /* AHB-to-APB Bridge Controller */ 44*4882a593Smuzhiyun #define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000 45*4882a593Smuzhiyun /* External AHB2AHB Controller */ 46*4882a593Smuzhiyun #define CONFIG_EXT_AHB2AHB_BASE 0x90E00000 47*4882a593Smuzhiyun /* Andes Multi-core Interrupt Controller */ 48*4882a593Smuzhiyun #define CONFIG_NCEMIC100_BASE 0x90F00000 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun * APB Device definitions 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun /* Compat Flash Controller */ 54*4882a593Smuzhiyun #define CONFIG_FTCFC010_BASE 0x94000000 55*4882a593Smuzhiyun /* APB - SSP (SPI) (without AC97) Controller */ 56*4882a593Smuzhiyun #define CONFIG_FTSSP010_01_BASE 0x94100000 57*4882a593Smuzhiyun /* UART1 - APB STUART Controller (UART0 in Linux) */ 58*4882a593Smuzhiyun #define CONFIG_FTUART010_01_BASE 0x94200000 59*4882a593Smuzhiyun /* FTSDC010 SD Controller */ 60*4882a593Smuzhiyun #define CONFIG_FTSDC010_BASE 0x94400000 61*4882a593Smuzhiyun /* APB - SSP with HDA/AC97 Controller */ 62*4882a593Smuzhiyun #define CONFIG_FTSSP010_02_BASE 0x94500000 63*4882a593Smuzhiyun /* UART2 - APB STUART Controller (UART1 in Linux) */ 64*4882a593Smuzhiyun #define CONFIG_FTUART010_02_BASE 0x94600000 65*4882a593Smuzhiyun /* PCU Controller */ 66*4882a593Smuzhiyun #define CONFIG_ANDES_PCU_BASE 0x94800000 67*4882a593Smuzhiyun /* FTTMR010 Timer */ 68*4882a593Smuzhiyun #define CONFIG_FTTMR010_BASE 0x94900000 69*4882a593Smuzhiyun /* Watch Dog Controller */ 70*4882a593Smuzhiyun #define CONFIG_FTWDT010_BASE 0x94A00000 71*4882a593Smuzhiyun /* FTRTC010 Real Time Clock */ 72*4882a593Smuzhiyun #define CONFIG_FTRTC010_BASE 0x98B00000 73*4882a593Smuzhiyun /* GPIO Controller */ 74*4882a593Smuzhiyun #define CONFIG_FTGPIO010_BASE 0x94C00000 75*4882a593Smuzhiyun /* I2C Controller */ 76*4882a593Smuzhiyun #define CONFIG_FTIIC010_BASE 0x94E00000 77*4882a593Smuzhiyun /* PWM - Pulse Width Modulator Controller */ 78*4882a593Smuzhiyun #define CONFIG_FTPWM010_BASE 0x94F00000 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Debug LED */ 81*4882a593Smuzhiyun #define CONFIG_DEBUG_LED 0x902FFFFC 82*4882a593Smuzhiyun /* Power Management Unit */ 83*4882a593Smuzhiyun #define CONFIG_FTPMU010_BASE 0x98100000 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* __AG102_H */ 86