1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Andes Technology Corporation 3*4882a593Smuzhiyun * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4*4882a593Smuzhiyun * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __AE3XX_H 10*4882a593Smuzhiyun #define __AE3XX_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Hardware register bases */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Static Memory Controller (SRAM) */ 15*4882a593Smuzhiyun #define CONFIG_FTSMC020_BASE 0xe0400000 16*4882a593Smuzhiyun /* DMA Controller */ 17*4882a593Smuzhiyun #define CONFIG_FTDMAC020_BASE 0xf0c00000 18*4882a593Smuzhiyun /* AHB-to-APB Bridge */ 19*4882a593Smuzhiyun #define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000 20*4882a593Smuzhiyun /* Reserved */ 21*4882a593Smuzhiyun #define CONFIG_RESERVED_01_BASE 0xe0500000 22*4882a593Smuzhiyun /* Reserved */ 23*4882a593Smuzhiyun #define CONFIG_RESERVED_02_BASE 0xf0800000 24*4882a593Smuzhiyun /* Reserved */ 25*4882a593Smuzhiyun #define CONFIG_RESERVED_03_BASE 0xf0900000 26*4882a593Smuzhiyun /* Ethernet */ 27*4882a593Smuzhiyun #define CONFIG_FTMAC100_BASE 0xe0100000 28*4882a593Smuzhiyun /* Reserved */ 29*4882a593Smuzhiyun #define CONFIG_RESERVED_04_BASE 0xf1000000 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* APB Device definitions */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* UART1 */ 34*4882a593Smuzhiyun #define CONFIG_FTUART010_01_BASE 0xf0200000 35*4882a593Smuzhiyun /* UART2 */ 36*4882a593Smuzhiyun #define CONFIG_FTUART010_02_BASE 0xf0300000 37*4882a593Smuzhiyun /* Counter/Timers */ 38*4882a593Smuzhiyun #define CONFIG_FTTMR010_BASE 0xf0400000 39*4882a593Smuzhiyun /* Watchdog Timer */ 40*4882a593Smuzhiyun #define CONFIG_FTWDT010_BASE 0xf0500000 41*4882a593Smuzhiyun /* Real Time Clock */ 42*4882a593Smuzhiyun #define CONFIG_FTRTC010_BASE 0xf0600000 43*4882a593Smuzhiyun /* GPIO */ 44*4882a593Smuzhiyun #define CONFIG_FTGPIO010_BASE 0xf0700000 45*4882a593Smuzhiyun /* I2C */ 46*4882a593Smuzhiyun #define CONFIG_FTIIC010_BASE 0xf0a00000 47*4882a593Smuzhiyun /* SD Controller */ 48*4882a593Smuzhiyun #define CONFIG_FTSDC010_BASE 0xf0e00000 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* The following address was not defined in Linux */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Synchronous Serial Port Controller (SSP) 01 */ 53*4882a593Smuzhiyun #define CONFIG_FTSSP010_01_BASE 0xf0d00000 54*4882a593Smuzhiyun #endif /* __AE3XX_H */ 55