1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2011 Andes Technology Corporation 3*4882a593Smuzhiyun * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4*4882a593Smuzhiyun * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun.pic 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun.text 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <common.h> 14*4882a593Smuzhiyun#include <config.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#include <asm/macro.h> 17*4882a593Smuzhiyun#include <generated/asm-offsets.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/* 20*4882a593Smuzhiyun * parameters for the SDRAM controller 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1) 23*4882a593Smuzhiyun#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2) 24*4882a593Smuzhiyun#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1) 25*4882a593Smuzhiyun#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2) 26*4882a593Smuzhiyun#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR) 27*4882a593Smuzhiyun#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1 30*4882a593Smuzhiyun#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2 31*4882a593Smuzhiyun#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1 32*4882a593Smuzhiyun#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR 35*4882a593Smuzhiyun#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun/* 39*4882a593Smuzhiyun * for Orca and Emerald 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun#define BOARD_ID_REG 0x104 42*4882a593Smuzhiyun#define BOARD_ID_FAMILY_MASK 0xfff000 43*4882a593Smuzhiyun#define BOARD_ID_FAMILY_V5 0x556000 44*4882a593Smuzhiyun#define BOARD_ID_FAMILY_K7 0x74b000 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun/* 47*4882a593Smuzhiyun * parameters for the static memory controller 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR) 50*4882a593Smuzhiyun#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG 53*4882a593Smuzhiyun#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun/* 56*4882a593Smuzhiyun * for Orca and Emerald 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4) 59*4882a593Smuzhiyun#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun/* 62*4882a593Smuzhiyun * parameters for the pmu controoler 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun/* 67*4882a593Smuzhiyun * numeric 7 segment display 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun.macro led, num 70*4882a593Smuzhiyun write32 CONFIG_DEBUG_LED, \num 71*4882a593Smuzhiyun.endm 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun/* 74*4882a593Smuzhiyun * Waiting for SDRAM to set up 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun.macro wait_sdram 77*4882a593Smuzhiyun li $r0, CONFIG_FTSDMC021_BASE 78*4882a593Smuzhiyun1: 79*4882a593Smuzhiyun lwi $r1, [$r0+FTSDMC021_CR2] 80*4882a593Smuzhiyun bnez $r1, 1b 81*4882a593Smuzhiyun.endm 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun.globl mem_init 84*4882a593Smuzhiyunmem_init: 85*4882a593Smuzhiyun move $r11, $lp 86*4882a593Smuzhiyun li $r0, SMC_BANK0_CR_A 87*4882a593Smuzhiyun lwi $r1, [$r0+#0x00] 88*4882a593Smuzhiyun ori $r1, $r1, 0x8f0 89*4882a593Smuzhiyun xori $r1, $r1, 0x8f0 90*4882a593Smuzhiyun /* 16-bit mode */ 91*4882a593Smuzhiyun ori $r1, $r1, 0x60 92*4882a593Smuzhiyun li $r2, 0x00153153 93*4882a593Smuzhiyun swi $r1, [$r0+#0x00] 94*4882a593Smuzhiyun swi $r2, [$r0+#0x04] 95*4882a593Smuzhiyun move $lp, $r11 96*4882a593Smuzhiyun ret 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun#ifndef CONFIG_SKIP_LOWLEVEL_INIT 99*4882a593Smuzhiyun.globl lowlevel_init 100*4882a593Smuzhiyunlowlevel_init: 101*4882a593Smuzhiyun move $r10, $lp 102*4882a593Smuzhiyun jal remap 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) 105*4882a593Smuzhiyun jal enable_fpu 106*4882a593Smuzhiyun#endif 107*4882a593Smuzhiyun ret $r10 108*4882a593Smuzhiyun 109*4882a593Smuzhiyunremap: 110*4882a593Smuzhiyun move $r11, $lp 111*4882a593Smuzhiyunrelo_base: 112*4882a593Smuzhiyun mfusr $r0, $pc 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun#ifdef CONFIG_MEM_REMAP 115*4882a593Smuzhiyun li $r4, 0x00000000 116*4882a593Smuzhiyun li $r5, 0x80000000 117*4882a593Smuzhiyun la $r6, _end@GOTOFF 118*4882a593Smuzhiyun1: 119*4882a593Smuzhiyun lmw.bim $r12, [$r5], $r19 120*4882a593Smuzhiyun smw.bim $r12, [$r4], $r19 121*4882a593Smuzhiyun blt $r5, $r6, 1b 122*4882a593Smuzhiyun#endif /* #ifdef CONFIG_MEM_REMAP */ 123*4882a593Smuzhiyun move $lp, $r11 124*4882a593Smuzhiyun2: 125*4882a593Smuzhiyun ret 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* 128*4882a593Smuzhiyun * enable_fpu: 129*4882a593Smuzhiyun * Some of Andes CPU version support FPU coprocessor, if so, 130*4882a593Smuzhiyun * and toolchain support FPU instruction set, we should enable it. 131*4882a593Smuzhiyun */ 132*4882a593Smuzhiyun#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) 133*4882a593Smuzhiyunenable_fpu: 134*4882a593Smuzhiyun mfsr $r0, $CPU_VER /* enable FPU if it exists */ 135*4882a593Smuzhiyun srli $r0, $r0, 3 136*4882a593Smuzhiyun andi $r0, $r0, 1 137*4882a593Smuzhiyun beqz $r0, 1f /* skip if no COP */ 138*4882a593Smuzhiyun mfsr $r0, $FUCOP_EXIST 139*4882a593Smuzhiyun srli $r0, $r0, 31 140*4882a593Smuzhiyun beqz $r0, 1f /* skip if no FPU */ 141*4882a593Smuzhiyun mfsr $r0, $FUCOP_CTL 142*4882a593Smuzhiyun ori $r0, $r0, 1 143*4882a593Smuzhiyun mtsr $r0, $FUCOP_CTL 144*4882a593Smuzhiyun1: 145*4882a593Smuzhiyun ret 146*4882a593Smuzhiyun#endif 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ 149