1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (c) 2015 Paul Thacker <paul.thacker@microchip.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __PIC32_REGS_H__ 9*4882a593Smuzhiyun #define __PIC32_REGS_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/io.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* System Configuration */ 14*4882a593Smuzhiyun #define PIC32_CFG_BASE 0x1f800000 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* System config register offsets */ 17*4882a593Smuzhiyun #define CFGCON 0x0000 18*4882a593Smuzhiyun #define DEVID 0x0020 19*4882a593Smuzhiyun #define SYSKEY 0x0030 20*4882a593Smuzhiyun #define PMD1 0x0040 21*4882a593Smuzhiyun #define PMD7 0x00a0 22*4882a593Smuzhiyun #define CFGEBIA 0x00c0 23*4882a593Smuzhiyun #define CFGEBIC 0x00d0 24*4882a593Smuzhiyun #define CFGPG 0x00e0 25*4882a593Smuzhiyun #define CFGMPLL 0x0100 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Non Volatile Memory (NOR flash) */ 28*4882a593Smuzhiyun #define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600) 29*4882a593Smuzhiyun /* Oscillator Configuration */ 30*4882a593Smuzhiyun #define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200) 31*4882a593Smuzhiyun /* Peripheral Pin Select Input */ 32*4882a593Smuzhiyun #define PPS_IN_BASE 0x1f801400 33*4882a593Smuzhiyun /* Peripheral Pin Select Output */ 34*4882a593Smuzhiyun #define PPS_OUT_BASE 0x1f801500 35*4882a593Smuzhiyun /* Pin Config */ 36*4882a593Smuzhiyun #define PINCTRL_BASE 0x1f860000 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* USB Core */ 39*4882a593Smuzhiyun #define PIC32_USB_CORE_BASE 0x1f8e3000 40*4882a593Smuzhiyun #define PIC32_USB_CTRL_BASE 0x1f884000 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* SPI1-SPI6 */ 43*4882a593Smuzhiyun #define PIC32_SPI1_BASE 0x1f821000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Prefetch Module */ 46*4882a593Smuzhiyun #define PREFETCH_BASE 0x1f8e0000 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* DDR2 Controller */ 49*4882a593Smuzhiyun #define PIC32_DDR2C_BASE 0x1f8e8000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* DDR2 PHY */ 52*4882a593Smuzhiyun #define PIC32_DDR2P_BASE 0x1f8e9100 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* EBI */ 55*4882a593Smuzhiyun #define PIC32_EBI_BASE 0x1f8e1000 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* SQI */ 58*4882a593Smuzhiyun #define PIC32_SQI_BASE 0x1f8e2000 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct pic32_reg_atomic { 61*4882a593Smuzhiyun u32 raw; 62*4882a593Smuzhiyun u32 clr; 63*4882a593Smuzhiyun u32 set; 64*4882a593Smuzhiyun u32 inv; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define _CLR_OFFSET 0x04 68*4882a593Smuzhiyun #define _SET_OFFSET 0x08 69*4882a593Smuzhiyun #define _INV_OFFSET 0x0c 70*4882a593Smuzhiyun pic32_get_syscfg_base(void)71*4882a593Smuzhiyunstatic inline void __iomem *pic32_get_syscfg_base(void) 72*4882a593Smuzhiyun { 73*4882a593Smuzhiyun return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE); 74*4882a593Smuzhiyun } 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Core */ 77*4882a593Smuzhiyun const char *get_core_name(void); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* __PIC32_REGS_H__ */ 80