1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * AU1X00 UART support
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Hardcoded to UART 0 for now
5*4882a593Smuzhiyun * Speed and options also hardcoded to 115200 8N1
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2003 Thomas.Lange@corelatus.se
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <config.h>
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include <mach/au1x00.h>
15*4882a593Smuzhiyun #include <serial.h>
16*4882a593Smuzhiyun #include <linux/compiler.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /******************************************************************************
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * serial_init - initialize a channel
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * This routine initializes the number of data bits, parity
23*4882a593Smuzhiyun * and set the selected baud rate. Interrupts are disabled.
24*4882a593Smuzhiyun * Set the modem control signals if the option is selected.
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun * RETURNS: N/A
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun
au1x00_serial_init(void)29*4882a593Smuzhiyun static int au1x00_serial_init(void)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
32*4882a593Smuzhiyun volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Enable clocks first */
35*4882a593Smuzhiyun *uart_enable = UART_EN_CE;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Then release reset */
38*4882a593Smuzhiyun /* Must release reset before setting other regs */
39*4882a593Smuzhiyun *uart_enable = UART_EN_CE|UART_EN_E;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* Activate fifos, reset tx and rx */
42*4882a593Smuzhiyun /* Set tx trigger level to 12 */
43*4882a593Smuzhiyun *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
44*4882a593Smuzhiyun UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun serial_setbrg();
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun
au1x00_serial_setbrg(void)52*4882a593Smuzhiyun static void au1x00_serial_setbrg(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
55*4882a593Smuzhiyun volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
56*4882a593Smuzhiyun volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
57*4882a593Smuzhiyun int sd;
58*4882a593Smuzhiyun int divisorx2;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* sd is system clock divisor */
61*4882a593Smuzhiyun /* see section 10.4.5 in au1550 datasheet */
62*4882a593Smuzhiyun sd = (*sys_powerctrl & 0x03) + 2;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* calulate 2x baudrate and round */
65*4882a593Smuzhiyun divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (divisorx2 & 0x01)
68*4882a593Smuzhiyun divisorx2 = divisorx2 + 1;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun *uart_clk = divisorx2 / 2;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Set parity, stop bits and word length to 8N1 */
73*4882a593Smuzhiyun *uart_lcr = UART_LCR_WLEN8;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
au1x00_serial_putc(const char c)76*4882a593Smuzhiyun static void au1x00_serial_putc(const char c)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
79*4882a593Smuzhiyun volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (c == '\n')
82*4882a593Smuzhiyun au1x00_serial_putc('\r');
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Wait for fifo to shift out some bytes */
85*4882a593Smuzhiyun while((*uart_lsr&UART_LSR_THRE)==0);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun *uart_tx = (u32)c;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
au1x00_serial_getc(void)90*4882a593Smuzhiyun static int au1x00_serial_getc(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
93*4882a593Smuzhiyun char c;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun while (!serial_tstc());
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun c = (*uart_rx&0xFF);
98*4882a593Smuzhiyun return c;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
au1x00_serial_tstc(void)101*4882a593Smuzhiyun static int au1x00_serial_tstc(void)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if(*uart_lsr&UART_LSR_DR){
106*4882a593Smuzhiyun /* Data in rfifo */
107*4882a593Smuzhiyun return(1);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun static struct serial_device au1x00_serial_drv = {
113*4882a593Smuzhiyun .name = "au1x00_serial",
114*4882a593Smuzhiyun .start = au1x00_serial_init,
115*4882a593Smuzhiyun .stop = NULL,
116*4882a593Smuzhiyun .setbrg = au1x00_serial_setbrg,
117*4882a593Smuzhiyun .putc = au1x00_serial_putc,
118*4882a593Smuzhiyun .puts = default_serial_puts,
119*4882a593Smuzhiyun .getc = au1x00_serial_getc,
120*4882a593Smuzhiyun .tstc = au1x00_serial_tstc,
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
au1x00_serial_initialize(void)123*4882a593Smuzhiyun void au1x00_serial_initialize(void)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun serial_register(&au1x00_serial_drv);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
default_serial_console(void)128*4882a593Smuzhiyun __weak struct serial_device *default_serial_console(void)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun return &au1x00_serial_drv;
131*4882a593Smuzhiyun }
132