1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3*4882a593Smuzhiyun * Copyright (C) 2013 Imagination Technologies 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _MIPS_ASM_MALTA_H 9*4882a593Smuzhiyun #define _MIPS_ASM_MALTA_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MALTA_GT_BASE 0x1be00000 12*4882a593Smuzhiyun #define MALTA_GT_PCIIO_BASE 0x18000000 13*4882a593Smuzhiyun #define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define MALTA_MSC01_BIU_BASE 0x1bc80000 16*4882a593Smuzhiyun #define MALTA_MSC01_PCI_BASE 0x1bd00000 17*4882a593Smuzhiyun #define MALTA_MSC01_PBC_BASE 0x1bd40000 18*4882a593Smuzhiyun #define MALTA_MSC01_IP1_BASE 0x1bc00000 19*4882a593Smuzhiyun #define MALTA_MSC01_IP1_SIZE 0x00400000 20*4882a593Smuzhiyun #define MALTA_MSC01_IP2_BASE1 0x10000000 21*4882a593Smuzhiyun #define MALTA_MSC01_IP2_SIZE1 0x08000000 22*4882a593Smuzhiyun #define MALTA_MSC01_IP2_BASE2 0x18000000 23*4882a593Smuzhiyun #define MALTA_MSC01_IP2_SIZE2 0x04000000 24*4882a593Smuzhiyun #define MALTA_MSC01_IP3_BASE 0x1c000000 25*4882a593Smuzhiyun #define MALTA_MSC01_IP3_SIZE 0x04000000 26*4882a593Smuzhiyun #define MALTA_MSC01_PCIMEM_BASE 0x10000000 27*4882a593Smuzhiyun #define MALTA_MSC01_PCIMEM_SIZE 0x10000000 28*4882a593Smuzhiyun #define MALTA_MSC01_PCIMEM_MAP 0x10000000 29*4882a593Smuzhiyun #define MALTA_MSC01_PCIIO_BASE 0x1b000000 30*4882a593Smuzhiyun #define MALTA_MSC01_PCIIO_SIZE 0x00800000 31*4882a593Smuzhiyun #define MALTA_MSC01_PCIIO_MAP 0x00000000 32*4882a593Smuzhiyun #define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define MALTA_ASCIIWORD 0x1f000410 35*4882a593Smuzhiyun #define MALTA_ASCIIPOS0 0x1f000418 36*4882a593Smuzhiyun #define MALTA_ASCIIPOS1 0x1f000420 37*4882a593Smuzhiyun #define MALTA_ASCIIPOS2 0x1f000428 38*4882a593Smuzhiyun #define MALTA_ASCIIPOS3 0x1f000430 39*4882a593Smuzhiyun #define MALTA_ASCIIPOS4 0x1f000438 40*4882a593Smuzhiyun #define MALTA_ASCIIPOS5 0x1f000440 41*4882a593Smuzhiyun #define MALTA_ASCIIPOS6 0x1f000448 42*4882a593Smuzhiyun #define MALTA_ASCIIPOS7 0x1f000450 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define MALTA_RESET_BASE 0x1f000500 45*4882a593Smuzhiyun #define GORESET 0x42 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MALTA_FLASH_BASE 0x1e000000 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define MALTA_REVISION 0x1fc00010 50*4882a593Smuzhiyun #define MALTA_REVISION_CORID_SHF 10 51*4882a593Smuzhiyun #define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF) 52*4882a593Smuzhiyun #define MALTA_REVISION_CORID_CORE_LV 1 53*4882a593Smuzhiyun #define MALTA_REVISION_CORID_CORE_FPGA6 14 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define PCI_CFG_PIIX4_PIRQRCA 0x60 56*4882a593Smuzhiyun #define PCI_CFG_PIIX4_PIRQRCB 0x61 57*4882a593Smuzhiyun #define PCI_CFG_PIIX4_PIRQRCC 0x62 58*4882a593Smuzhiyun #define PCI_CFG_PIIX4_PIRQRCD 0x63 59*4882a593Smuzhiyun #define PCI_CFG_PIIX4_SERIRQC 0x64 60*4882a593Smuzhiyun #define PCI_CFG_PIIX4_GENCFG 0xb0 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7) 63*4882a593Smuzhiyun #define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define PCI_CFG_PIIX4_IDETIM_PRI 0x40 68*4882a593Smuzhiyun #define PCI_CFG_PIIX4_IDETIM_SEC 0x42 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define PCI_CFG_PIIX4_IDETIM_IDE (1 << 15) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* _MIPS_ASM_MALTA_H */ 73