1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * MIPS Coherence Manager (CM) Register Definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2016 Imagination Technologies Ltd. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __MIPS_ASM_CM_H__ 9*4882a593Smuzhiyun #define __MIPS_ASM_CM_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Global Control Register (GCR) offsets */ 12*4882a593Smuzhiyun #define GCR_BASE 0x0008 13*4882a593Smuzhiyun #define GCR_BASE_UPPER 0x000c 14*4882a593Smuzhiyun #define GCR_REV 0x0030 15*4882a593Smuzhiyun #define GCR_L2_CONFIG 0x0130 16*4882a593Smuzhiyun #define GCR_L2_TAG_ADDR 0x0600 17*4882a593Smuzhiyun #define GCR_L2_TAG_ADDR_UPPER 0x0604 18*4882a593Smuzhiyun #define GCR_L2_TAG_STATE 0x0608 19*4882a593Smuzhiyun #define GCR_L2_TAG_STATE_UPPER 0x060c 20*4882a593Smuzhiyun #define GCR_L2_DATA 0x0610 21*4882a593Smuzhiyun #define GCR_L2_DATA_UPPER 0x0614 22*4882a593Smuzhiyun #define GCR_Cx_COHERENCE 0x2008 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* GCR_REV CM versions */ 25*4882a593Smuzhiyun #define GCR_REV_CM3 0x0800 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* GCR_L2_CONFIG fields */ 28*4882a593Smuzhiyun #define GCR_L2_CONFIG_ASSOC_SHIFT 0 29*4882a593Smuzhiyun #define GCR_L2_CONFIG_ASSOC_BITS 8 30*4882a593Smuzhiyun #define GCR_L2_CONFIG_LINESZ_SHIFT 8 31*4882a593Smuzhiyun #define GCR_L2_CONFIG_LINESZ_BITS 4 32*4882a593Smuzhiyun #define GCR_L2_CONFIG_SETSZ_SHIFT 12 33*4882a593Smuzhiyun #define GCR_L2_CONFIG_SETSZ_BITS 4 34*4882a593Smuzhiyun #define GCR_L2_CONFIG_BYPASS (1 << 20) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* GCR_Cx_COHERENCE */ 37*4882a593Smuzhiyun #define GCR_Cx_COHERENCE_DOM_EN (0xff << 0) 38*4882a593Smuzhiyun #define GCR_Cx_COHERENCE_EN (0x1 << 0) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #include <asm/io.h> 43*4882a593Smuzhiyun mips_cm_base(void)44*4882a593Smuzhiyunstatic inline void *mips_cm_base(void) 45*4882a593Smuzhiyun { 46*4882a593Smuzhiyun return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); 47*4882a593Smuzhiyun } 48*4882a593Smuzhiyun mips_cm_l2_line_size(void)49*4882a593Smuzhiyunstatic inline unsigned long mips_cm_l2_line_size(void) 50*4882a593Smuzhiyun { 51*4882a593Smuzhiyun unsigned long l2conf, line_sz; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT; 56*4882a593Smuzhiyun line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); 57*4882a593Smuzhiyun return line_sz ? (2 << line_sz) : 0; 58*4882a593Smuzhiyun } 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif /* __MIPS_ASM_CM_H__ */ 63