1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Cache operations for the cache instruction.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
5*4882a593Smuzhiyun * (C) Copyright 1999 Silicon Graphics, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #ifndef __ASM_CACHEOPS_H
10*4882a593Smuzhiyun #define __ASM_CACHEOPS_H
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifndef __ASSEMBLY__
13*4882a593Smuzhiyun
mips_cache(int op,const volatile void * addr)14*4882a593Smuzhiyun static inline void mips_cache(int op, const volatile void *addr)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
17*4882a593Smuzhiyun __builtin_mips_cache(op, addr);
18*4882a593Smuzhiyun #else
19*4882a593Smuzhiyun __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
20*4882a593Smuzhiyun #endif
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * Cache Operations available on all MIPS processors with R4000-style caches
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun #define INDEX_INVALIDATE_I 0x00
29*4882a593Smuzhiyun #define INDEX_WRITEBACK_INV_D 0x01
30*4882a593Smuzhiyun #define INDEX_LOAD_TAG_I 0x04
31*4882a593Smuzhiyun #define INDEX_LOAD_TAG_D 0x05
32*4882a593Smuzhiyun #define INDEX_STORE_TAG_I 0x08
33*4882a593Smuzhiyun #define INDEX_STORE_TAG_D 0x09
34*4882a593Smuzhiyun #if defined(CONFIG_CPU_LOONGSON2)
35*4882a593Smuzhiyun #define HIT_INVALIDATE_I 0x00
36*4882a593Smuzhiyun #else
37*4882a593Smuzhiyun #define HIT_INVALIDATE_I 0x10
38*4882a593Smuzhiyun #endif
39*4882a593Smuzhiyun #define HIT_INVALIDATE_D 0x11
40*4882a593Smuzhiyun #define HIT_WRITEBACK_INV_D 0x15
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * R4000-specific cacheops
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun #define CREATE_DIRTY_EXCL_D 0x0d
46*4882a593Smuzhiyun #define FILL 0x14
47*4882a593Smuzhiyun #define HIT_WRITEBACK_I 0x18
48*4882a593Smuzhiyun #define HIT_WRITEBACK_D 0x19
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun * R4000SC and R4400SC-specific cacheops
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun #define INDEX_INVALIDATE_SI 0x02
54*4882a593Smuzhiyun #define INDEX_WRITEBACK_INV_SD 0x03
55*4882a593Smuzhiyun #define INDEX_LOAD_TAG_SI 0x06
56*4882a593Smuzhiyun #define INDEX_LOAD_TAG_SD 0x07
57*4882a593Smuzhiyun #define INDEX_STORE_TAG_SI 0x0A
58*4882a593Smuzhiyun #define INDEX_STORE_TAG_SD 0x0B
59*4882a593Smuzhiyun #define CREATE_DIRTY_EXCL_SD 0x0f
60*4882a593Smuzhiyun #define HIT_INVALIDATE_SI 0x12
61*4882a593Smuzhiyun #define HIT_INVALIDATE_SD 0x13
62*4882a593Smuzhiyun #define HIT_WRITEBACK_INV_SD 0x17
63*4882a593Smuzhiyun #define HIT_WRITEBACK_SD 0x1b
64*4882a593Smuzhiyun #define HIT_SET_VIRTUAL_SI 0x1e
65*4882a593Smuzhiyun #define HIT_SET_VIRTUAL_SD 0x1f
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /*
68*4882a593Smuzhiyun * R5000-specific cacheops
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun #define R5K_PAGE_INVALIDATE_S 0x17
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /*
73*4882a593Smuzhiyun * RM7000-specific cacheops
74*4882a593Smuzhiyun */
75*4882a593Smuzhiyun #define PAGE_INVALIDATE_T 0x16
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * R10000-specific cacheops
79*4882a593Smuzhiyun *
80*4882a593Smuzhiyun * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
81*4882a593Smuzhiyun * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
82*4882a593Smuzhiyun */
83*4882a593Smuzhiyun #define INDEX_WRITEBACK_INV_S 0x03
84*4882a593Smuzhiyun #define INDEX_LOAD_TAG_S 0x07
85*4882a593Smuzhiyun #define INDEX_STORE_TAG_S 0x0B
86*4882a593Smuzhiyun #define HIT_INVALIDATE_S 0x13
87*4882a593Smuzhiyun #define CACHE_BARRIER 0x14
88*4882a593Smuzhiyun #define HIT_WRITEBACK_INV_S 0x17
89*4882a593Smuzhiyun #define INDEX_LOAD_DATA_I 0x18
90*4882a593Smuzhiyun #define INDEX_LOAD_DATA_D 0x19
91*4882a593Smuzhiyun #define INDEX_LOAD_DATA_S 0x1b
92*4882a593Smuzhiyun #define INDEX_STORE_DATA_I 0x1c
93*4882a593Smuzhiyun #define INDEX_STORE_DATA_D 0x1d
94*4882a593Smuzhiyun #define INDEX_STORE_DATA_S 0x1f
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #endif /* __ASM_CACHEOPS_H */
97