1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2011 The Chromium OS Authors. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MIPS_CACHE_H__ 8*4882a593Smuzhiyun #define __MIPS_CACHE_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT 11*4882a593Smuzhiyun #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for 17*4882a593Smuzhiyun * DMA buffer alignment. Satisfy those drivers by providing it as a synonym 18*4882a593Smuzhiyun * of ARCH_DMA_MINALIGN for now. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 23*4882a593Smuzhiyun /** 24*4882a593Smuzhiyun * mips_cache_probe() - Probe the properties of the caches 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * Call this to probe the properties such as line sizes of the caches 27*4882a593Smuzhiyun * present in the system, if any. This must be done before cache maintenance 28*4882a593Smuzhiyun * functions such as flush_cache may be called. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun void mips_cache_probe(void); 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* __MIPS_CACHE_H__ */ 34