1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 1996, 99, 2003 by Ralf Baechle
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #ifndef _ASM_BYTEORDER_H
7*4882a593Smuzhiyun #define _ASM_BYTEORDER_H
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <asm/types.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #ifdef __GNUC__
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #ifdef CONFIG_CPU_MIPSR2
14*4882a593Smuzhiyun
___arch__swab16(__u16 x)15*4882a593Smuzhiyun static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun __asm__(
18*4882a593Smuzhiyun " wsbh %0, %1 \n"
19*4882a593Smuzhiyun : "=r" (x)
20*4882a593Smuzhiyun : "r" (x));
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun return x;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun #define __arch__swab16(x) ___arch__swab16(x)
25*4882a593Smuzhiyun
___arch__swab32(__u32 x)26*4882a593Smuzhiyun static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun __asm__(
29*4882a593Smuzhiyun " wsbh %0, %1 \n"
30*4882a593Smuzhiyun " rotr %0, %0, 16 \n"
31*4882a593Smuzhiyun : "=r" (x)
32*4882a593Smuzhiyun : "r" (x));
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return x;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun #define __arch__swab32(x) ___arch__swab32(x)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #ifdef CONFIG_CPU_MIPS64_R2
39*4882a593Smuzhiyun
___arch__swab64(__u64 x)40*4882a593Smuzhiyun static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun __asm__(
43*4882a593Smuzhiyun " dsbh %0, %1 \n"
44*4882a593Smuzhiyun " dshd %0, %0 \n"
45*4882a593Smuzhiyun " drotr %0, %0, 32 \n"
46*4882a593Smuzhiyun : "=r" (x)
47*4882a593Smuzhiyun : "r" (x));
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return x;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define __arch__swab64(x) ___arch__swab64(x)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #endif /* CONFIG_CPU_MIPS64_R2 */
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #endif /* CONFIG_CPU_MIPSR2 */
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
59*4882a593Smuzhiyun # define __BYTEORDER_HAS_U64__
60*4882a593Smuzhiyun # define __SWAB_64_THRU_32__
61*4882a593Smuzhiyun #endif
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #endif /* __GNUC__ */
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #if defined(__MIPSEB__)
66*4882a593Smuzhiyun # include <linux/byteorder/big_endian.h>
67*4882a593Smuzhiyun #elif defined(__MIPSEL__)
68*4882a593Smuzhiyun # include <linux/byteorder/little_endian.h>
69*4882a593Smuzhiyun #else
70*4882a593Smuzhiyun # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
71*4882a593Smuzhiyun #endif
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #endif /* _ASM_BYTEORDER_H */
74