1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 8*4882a593Smuzhiyun#include "skeleton.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun compatible = "qca,qca953x"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #address-cells = <1>; 14*4882a593Smuzhiyun #size-cells = <1>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun cpus { 17*4882a593Smuzhiyun #address-cells = <1>; 18*4882a593Smuzhiyun #size-cells = <0>; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun cpu@0 { 21*4882a593Smuzhiyun device_type = "cpu"; 22*4882a593Smuzhiyun compatible = "mips,mips24Kc"; 23*4882a593Smuzhiyun reg = <0>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun clocks { 28*4882a593Smuzhiyun #address-cells = <1>; 29*4882a593Smuzhiyun #size-cells = <1>; 30*4882a593Smuzhiyun ranges; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun xtal: xtal { 33*4882a593Smuzhiyun #clock-cells = <0>; 34*4882a593Smuzhiyun compatible = "fixed-clock"; 35*4882a593Smuzhiyun clock-output-names = "xtal"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun pinctrl { 40*4882a593Smuzhiyun u-boot,dm-pre-reloc; 41*4882a593Smuzhiyun compatible = "qca,qca953x-pinctrl"; 42*4882a593Smuzhiyun ranges; 43*4882a593Smuzhiyun #address-cells = <1>; 44*4882a593Smuzhiyun #size-cells = <1>; 45*4882a593Smuzhiyun reg = <0x18040000 0x100>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun ahb { 49*4882a593Smuzhiyun compatible = "simple-bus"; 50*4882a593Smuzhiyun ranges; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #address-cells = <1>; 53*4882a593Smuzhiyun #size-cells = <1>; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun apb { 56*4882a593Smuzhiyun compatible = "simple-bus"; 57*4882a593Smuzhiyun ranges; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #address-cells = <1>; 60*4882a593Smuzhiyun #size-cells = <1>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun uart0: uart@18020000 { 63*4882a593Smuzhiyun compatible = "ns16550"; 64*4882a593Smuzhiyun reg = <0x18020000 0x20>; 65*4882a593Smuzhiyun reg-shift = <2>; 66*4882a593Smuzhiyun clock-frequency = <25000000>; 67*4882a593Smuzhiyun interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun status = "disabled"; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun spi0: spi@1f000000 { 74*4882a593Smuzhiyun compatible = "qca,ar7100-spi"; 75*4882a593Smuzhiyun reg = <0x1f000000 0x10>; 76*4882a593Smuzhiyun interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun status = "disabled"; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #address-cells = <1>; 81*4882a593Smuzhiyun #size-cells = <0>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun}; 85