1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2015 Microchip Technology, Inc. 3*4882a593Smuzhiyun * Purna Chandra Mandal, <purna.mandal@microchip.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 9*4882a593Smuzhiyun#include <dt-bindings/clock/microchip,clock.h> 10*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 11*4882a593Smuzhiyun#include "skeleton.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun compatible = "microchip,pic32mzda", "microchip,pic32mz"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun gpio0 = &gpioA; 18*4882a593Smuzhiyun gpio1 = &gpioB; 19*4882a593Smuzhiyun gpio2 = &gpioC; 20*4882a593Smuzhiyun gpio3 = &gpioD; 21*4882a593Smuzhiyun gpio4 = &gpioE; 22*4882a593Smuzhiyun gpio5 = &gpioF; 23*4882a593Smuzhiyun gpio6 = &gpioG; 24*4882a593Smuzhiyun gpio7 = &gpioH; 25*4882a593Smuzhiyun gpio8 = &gpioJ; 26*4882a593Smuzhiyun gpio9 = &gpioK; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun cpus { 30*4882a593Smuzhiyun cpu@0 { 31*4882a593Smuzhiyun compatible = "mips,mips14kc"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clock: clk@1f801200 { 36*4882a593Smuzhiyun compatible = "microchip,pic32mzda-clk"; 37*4882a593Smuzhiyun reg = <0x1f801200 0x1000>; 38*4882a593Smuzhiyun #clock-cells = <1>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun uart1: serial@1f822000 { 42*4882a593Smuzhiyun compatible = "microchip,pic32mzda-uart"; 43*4882a593Smuzhiyun reg = <0x1f822000 0x50>; 44*4882a593Smuzhiyun interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; 45*4882a593Smuzhiyun status = "disabled"; 46*4882a593Smuzhiyun clocks = <&clock PB2CLK>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun uart2: serial@1f822200 { 50*4882a593Smuzhiyun compatible = "microchip,pic32mzda-uart"; 51*4882a593Smuzhiyun reg = <0x1f822200 0x50>; 52*4882a593Smuzhiyun interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; 53*4882a593Smuzhiyun clocks = <&clock PB2CLK>; 54*4882a593Smuzhiyun status = "disabled"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun uart6: serial@1f822a00 { 58*4882a593Smuzhiyun compatible = "microchip,pic32mzda-uart"; 59*4882a593Smuzhiyun reg = <0x1f822a00 0x50>; 60*4882a593Smuzhiyun interrupts = <188 IRQ_TYPE_LEVEL_HIGH>; 61*4882a593Smuzhiyun clocks = <&clock PB2CLK>; 62*4882a593Smuzhiyun status = "disabled"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun evic: interrupt-controller@1f810000 { 66*4882a593Smuzhiyun compatible = "microchip,pic32mzda-evic"; 67*4882a593Smuzhiyun interrupt-controller; 68*4882a593Smuzhiyun #interrupt-cells = <2>; 69*4882a593Smuzhiyun reg = <0x1f810000 0x1000>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun pinctrl: pinctrl@1f801400 { 73*4882a593Smuzhiyun compatible = "microchip,pic32mzda-pinctrl"; 74*4882a593Smuzhiyun reg = <0x1f801400 0x100>, /* in */ 75*4882a593Smuzhiyun <0x1f801500 0x200>, /* out */ 76*4882a593Smuzhiyun <0x1f860000 0xa00>; /* port */ 77*4882a593Smuzhiyun reg-names = "ppsin","ppsout","port"; 78*4882a593Smuzhiyun status = "disabled"; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun ranges = <0 0x1f860000 0xa00>; 81*4882a593Smuzhiyun #address-cells = <1>; 82*4882a593Smuzhiyun #size-cells = <1>; 83*4882a593Smuzhiyun gpioA: gpio0@0 { 84*4882a593Smuzhiyun compatible = "microchip,pic32mzda-gpio"; 85*4882a593Smuzhiyun reg = <0x000 0x48>; 86*4882a593Smuzhiyun gpio-controller; 87*4882a593Smuzhiyun #gpio-cells = <2>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun gpioB: gpio1@100 { 91*4882a593Smuzhiyun compatible = "microchip,pic32mzda-gpio"; 92*4882a593Smuzhiyun reg = <0x100 0x48>; 93*4882a593Smuzhiyun gpio-controller; 94*4882a593Smuzhiyun #gpio-cells = <2>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun gpioC: gpio2@200 { 98*4882a593Smuzhiyun compatible = "microchip,pic32mzda-gpio"; 99*4882a593Smuzhiyun reg = <0x200 0x48>; 100*4882a593Smuzhiyun gpio-controller; 101*4882a593Smuzhiyun #gpio-cells = <2>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun gpioD: gpio3@300 { 105*4882a593Smuzhiyun compatible = "microchip,pic32mzda-gpio"; 106*4882a593Smuzhiyun reg = <0x300 0x48>; 107*4882a593Smuzhiyun gpio-controller; 108*4882a593Smuzhiyun #gpio-cells = <2>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun gpioE: gpio4@400 { 112*4882a593Smuzhiyun compatible = "microchip,pic32mzda-gpio"; 113*4882a593Smuzhiyun reg = <0x400 0x48>; 114*4882a593Smuzhiyun gpio-controller; 115*4882a593Smuzhiyun #gpio-cells = <2>; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun gpioF: gpio5@500 { 119*4882a593Smuzhiyun compatible = "microchip,pic32mzda-gpio"; 120*4882a593Smuzhiyun reg = <0x500 0x48>; 121*4882a593Smuzhiyun gpio-controller; 122*4882a593Smuzhiyun #gpio-cells = <2>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun gpioG: gpio6@600 { 126*4882a593Smuzhiyun compatible = "microchip,pic32mzda-gpio"; 127*4882a593Smuzhiyun reg = <0x600 0x48>; 128*4882a593Smuzhiyun gpio-controller; 129*4882a593Smuzhiyun #gpio-cells = <2>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun gpioH: gpio7@700 { 133*4882a593Smuzhiyun compatible = "microchip,pic32mzda-gpio"; 134*4882a593Smuzhiyun reg = <0x700 0x48>; 135*4882a593Smuzhiyun gpio-controller; 136*4882a593Smuzhiyun #gpio-cells = <2>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun gpioJ: gpio8@800 { 140*4882a593Smuzhiyun compatible = "microchip,pic32mzda-gpio"; 141*4882a593Smuzhiyun reg = <0x800 0x48>; 142*4882a593Smuzhiyun gpio-controller; 143*4882a593Smuzhiyun #gpio-cells = <2>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun gpioK: gpio9@900 { 147*4882a593Smuzhiyun compatible = "microchip,pic32mzda-gpio"; 148*4882a593Smuzhiyun reg = <0x900 0x48>; 149*4882a593Smuzhiyun gpio-controller; 150*4882a593Smuzhiyun #gpio-cells = <2>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun sdhci: sdhci@1f8ec000 { 155*4882a593Smuzhiyun compatible = "microchip,pic32mzda-sdhci"; 156*4882a593Smuzhiyun reg = <0x1f8ec000 0x100>; 157*4882a593Smuzhiyun interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; 158*4882a593Smuzhiyun clocks = <&clock REF4CLK>, <&clock PB5CLK>; 159*4882a593Smuzhiyun clock-names = "base_clk", "sys_clk"; 160*4882a593Smuzhiyun clock-freq-min-max = <25000000>,<25000000>; 161*4882a593Smuzhiyun bus-width = <4>; 162*4882a593Smuzhiyun status = "disabled"; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun ethernet: ethernet@1f882000 { 166*4882a593Smuzhiyun compatible = "microchip,pic32mzda-eth"; 167*4882a593Smuzhiyun reg = <0x1f882000 0x1000>; 168*4882a593Smuzhiyun interrupts = <153 IRQ_TYPE_LEVEL_HIGH>; 169*4882a593Smuzhiyun clocks = <&clock PB5CLK>; 170*4882a593Smuzhiyun status = "disabled"; 171*4882a593Smuzhiyun #address-cells = <1>; 172*4882a593Smuzhiyun #size-cells = <0>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun usb: musb@1f8e3000 { 176*4882a593Smuzhiyun compatible = "microchip,pic32mzda-usb"; 177*4882a593Smuzhiyun reg = <0x1f8e3000 0x1000>, 178*4882a593Smuzhiyun <0x1f884000 0x1000>; 179*4882a593Smuzhiyun reg-names = "mc", "control"; 180*4882a593Smuzhiyun interrupts = <132 IRQ_TYPE_EDGE_RISING>, 181*4882a593Smuzhiyun <133 IRQ_TYPE_LEVEL_HIGH>; 182*4882a593Smuzhiyun clocks = <&clock PB5CLK>; 183*4882a593Smuzhiyun clock-names = "usb_clk"; 184*4882a593Smuzhiyun status = "disabled"; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun}; 187