1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/clock/bcm6358-clock.h> 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include <dt-bindings/reset/bcm6358-reset.h> 10*4882a593Smuzhiyun#include "skeleton.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "brcm,bcm6358"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun cpus { 16*4882a593Smuzhiyun reg = <0xfffe0000 0x4>; 17*4882a593Smuzhiyun #address-cells = <1>; 18*4882a593Smuzhiyun #size-cells = <0>; 19*4882a593Smuzhiyun u-boot,dm-pre-reloc; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun cpu@0 { 22*4882a593Smuzhiyun compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; 23*4882a593Smuzhiyun device_type = "cpu"; 24*4882a593Smuzhiyun reg = <0>; 25*4882a593Smuzhiyun u-boot,dm-pre-reloc; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun cpu@1 { 29*4882a593Smuzhiyun compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; 30*4882a593Smuzhiyun device_type = "cpu"; 31*4882a593Smuzhiyun reg = <1>; 32*4882a593Smuzhiyun u-boot,dm-pre-reloc; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clocks { 37*4882a593Smuzhiyun compatible = "simple-bus"; 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <1>; 40*4882a593Smuzhiyun u-boot,dm-pre-reloc; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun periph_osc: periph-osc { 43*4882a593Smuzhiyun compatible = "fixed-clock"; 44*4882a593Smuzhiyun #clock-cells = <0>; 45*4882a593Smuzhiyun clock-frequency = <50000000>; 46*4882a593Smuzhiyun u-boot,dm-pre-reloc; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun periph_clk: periph-clk { 50*4882a593Smuzhiyun compatible = "brcm,bcm6345-clk"; 51*4882a593Smuzhiyun reg = <0xfffe0004 0x4>; 52*4882a593Smuzhiyun #clock-cells = <1>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun pflash: nor@1e000000 { 57*4882a593Smuzhiyun compatible = "cfi-flash"; 58*4882a593Smuzhiyun reg = <0x1e000000 0x2000000>; 59*4882a593Smuzhiyun bank-width = <2>; 60*4882a593Smuzhiyun #address-cells = <1>; 61*4882a593Smuzhiyun #size-cells = <1>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun status = "disabled"; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun ubus { 67*4882a593Smuzhiyun compatible = "simple-bus"; 68*4882a593Smuzhiyun #address-cells = <1>; 69*4882a593Smuzhiyun #size-cells = <1>; 70*4882a593Smuzhiyun u-boot,dm-pre-reloc; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun pll_cntl: syscon@fffe0008 { 73*4882a593Smuzhiyun compatible = "syscon"; 74*4882a593Smuzhiyun reg = <0xfffe0008 0x4>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun syscon-reboot { 78*4882a593Smuzhiyun compatible = "syscon-reboot"; 79*4882a593Smuzhiyun regmap = <&pll_cntl>; 80*4882a593Smuzhiyun offset = <0x0>; 81*4882a593Smuzhiyun mask = <0x1>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun periph_rst: reset-controller@fffe0034 { 85*4882a593Smuzhiyun compatible = "brcm,bcm6345-reset"; 86*4882a593Smuzhiyun reg = <0xfffe0034 0x4>; 87*4882a593Smuzhiyun #reset-cells = <1>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun wdt: watchdog@fffe005c { 91*4882a593Smuzhiyun compatible = "brcm,bcm6345-wdt"; 92*4882a593Smuzhiyun reg = <0xfffe005c 0xc>; 93*4882a593Smuzhiyun clocks = <&periph_osc>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun wdt-reboot { 97*4882a593Smuzhiyun compatible = "wdt-reboot"; 98*4882a593Smuzhiyun wdt = <&wdt>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun gpio1: gpio-controller@fffe0080 { 102*4882a593Smuzhiyun compatible = "brcm,bcm6345-gpio"; 103*4882a593Smuzhiyun reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>; 104*4882a593Smuzhiyun gpio-controller; 105*4882a593Smuzhiyun #gpio-cells = <2>; 106*4882a593Smuzhiyun ngpios = <8>; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun status = "disabled"; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun gpio0: gpio-controller@fffe0084 { 112*4882a593Smuzhiyun compatible = "brcm,bcm6345-gpio"; 113*4882a593Smuzhiyun reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>; 114*4882a593Smuzhiyun gpio-controller; 115*4882a593Smuzhiyun #gpio-cells = <2>; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun status = "disabled"; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun leds: led-controller@fffe00d0 { 121*4882a593Smuzhiyun compatible = "brcm,bcm6358-leds"; 122*4882a593Smuzhiyun reg = <0xfffe00d0 0x8>; 123*4882a593Smuzhiyun #address-cells = <1>; 124*4882a593Smuzhiyun #size-cells = <0>; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun status = "disabled"; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun uart0: serial@fffe0100 { 130*4882a593Smuzhiyun compatible = "brcm,bcm6345-uart"; 131*4882a593Smuzhiyun reg = <0xfffe0100 0x18>; 132*4882a593Smuzhiyun clocks = <&periph_osc>; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun status = "disabled"; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun uart1: serial@fffe0120 { 138*4882a593Smuzhiyun compatible = "brcm,bcm6345-uart"; 139*4882a593Smuzhiyun reg = <0xfffe0120 0x18>; 140*4882a593Smuzhiyun clocks = <&periph_osc>; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun status = "disabled"; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun memory-controller@fffe1200 { 146*4882a593Smuzhiyun compatible = "brcm,bcm6358-mc"; 147*4882a593Smuzhiyun reg = <0xfffe1200 0x4c>; 148*4882a593Smuzhiyun u-boot,dm-pre-reloc; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun}; 152