1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/clock/bcm6348-clock.h> 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include <dt-bindings/reset/bcm6348-reset.h> 10*4882a593Smuzhiyun#include "skeleton.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "brcm,bcm6348"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun cpus { 16*4882a593Smuzhiyun reg = <0xfffe0000 0x4>; 17*4882a593Smuzhiyun #address-cells = <1>; 18*4882a593Smuzhiyun #size-cells = <0>; 19*4882a593Smuzhiyun u-boot,dm-pre-reloc; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun cpu@0 { 22*4882a593Smuzhiyun compatible = "brcm,bcm6348-cpu", "mips,mips4Kc"; 23*4882a593Smuzhiyun device_type = "cpu"; 24*4882a593Smuzhiyun reg = <0>; 25*4882a593Smuzhiyun u-boot,dm-pre-reloc; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clocks { 30*4882a593Smuzhiyun compatible = "simple-bus"; 31*4882a593Smuzhiyun #address-cells = <1>; 32*4882a593Smuzhiyun #size-cells = <1>; 33*4882a593Smuzhiyun u-boot,dm-pre-reloc; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun periph_osc: periph-osc { 36*4882a593Smuzhiyun compatible = "fixed-clock"; 37*4882a593Smuzhiyun #clock-cells = <0>; 38*4882a593Smuzhiyun clock-frequency = <50000000>; 39*4882a593Smuzhiyun u-boot,dm-pre-reloc; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun periph_clk: periph-clk { 43*4882a593Smuzhiyun compatible = "brcm,bcm6345-clk"; 44*4882a593Smuzhiyun reg = <0xfffe0004 0x4>; 45*4882a593Smuzhiyun #clock-cells = <1>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun pflash: nor@1fc00000 { 50*4882a593Smuzhiyun compatible = "cfi-flash"; 51*4882a593Smuzhiyun reg = <0x1fc00000 0x2000000>; 52*4882a593Smuzhiyun bank-width = <2>; 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <1>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun status = "disabled"; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun ubus { 60*4882a593Smuzhiyun compatible = "simple-bus"; 61*4882a593Smuzhiyun #address-cells = <1>; 62*4882a593Smuzhiyun #size-cells = <1>; 63*4882a593Smuzhiyun u-boot,dm-pre-reloc; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun pll_cntl: syscon@fffe0008 { 66*4882a593Smuzhiyun compatible = "syscon"; 67*4882a593Smuzhiyun reg = <0xfffe0008 0x4>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun syscon-reboot { 71*4882a593Smuzhiyun compatible = "syscon-reboot"; 72*4882a593Smuzhiyun regmap = <&pll_cntl>; 73*4882a593Smuzhiyun offset = <0x0>; 74*4882a593Smuzhiyun mask = <0x1>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun periph_rst: reset-controller@fffe0028 { 78*4882a593Smuzhiyun compatible = "brcm,bcm6345-reset"; 79*4882a593Smuzhiyun reg = <0xfffe0028 0x4>; 80*4882a593Smuzhiyun #reset-cells = <1>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun wdt: watchdog@fffe021c { 84*4882a593Smuzhiyun compatible = "brcm,bcm6345-wdt"; 85*4882a593Smuzhiyun reg = <0xfffe021c 0xc>; 86*4882a593Smuzhiyun clocks = <&periph_osc>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun wdt-reboot { 90*4882a593Smuzhiyun compatible = "wdt-reboot"; 91*4882a593Smuzhiyun wdt = <&wdt>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun uart0: serial@fffe0300 { 95*4882a593Smuzhiyun compatible = "brcm,bcm6345-uart"; 96*4882a593Smuzhiyun reg = <0xfffe0300 0x18>; 97*4882a593Smuzhiyun clocks = <&periph_osc>; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun status = "disabled"; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun gpio1: gpio-controller@fffe0400 { 103*4882a593Smuzhiyun compatible = "brcm,bcm6345-gpio"; 104*4882a593Smuzhiyun reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>; 105*4882a593Smuzhiyun gpio-controller; 106*4882a593Smuzhiyun #gpio-cells = <2>; 107*4882a593Smuzhiyun ngpios = <5>; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun status = "disabled"; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun gpio0: gpio-controller@fffe0404 { 113*4882a593Smuzhiyun compatible = "brcm,bcm6345-gpio"; 114*4882a593Smuzhiyun reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>; 115*4882a593Smuzhiyun gpio-controller; 116*4882a593Smuzhiyun #gpio-cells = <2>; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun status = "disabled"; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun memory-controller@fffe2300 { 122*4882a593Smuzhiyun compatible = "brcm,bcm6338-mc"; 123*4882a593Smuzhiyun reg = <0xfffe2300 0x38>; 124*4882a593Smuzhiyun u-boot,dm-pre-reloc; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun}; 128