1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2016 Marek Vasut <marex@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "skeleton.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun compatible = "qca,ar934x"; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <1>; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun cpus { 16*4882a593Smuzhiyun #address-cells = <1>; 17*4882a593Smuzhiyun #size-cells = <0>; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun cpu@0 { 20*4882a593Smuzhiyun device_type = "cpu"; 21*4882a593Smuzhiyun compatible = "mips,mips74Kc"; 22*4882a593Smuzhiyun reg = <0>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clocks { 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <1>; 29*4882a593Smuzhiyun ranges; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun xtal: xtal { 32*4882a593Smuzhiyun #clock-cells = <0>; 33*4882a593Smuzhiyun compatible = "fixed-clock"; 34*4882a593Smuzhiyun clock-output-names = "xtal"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun ahb { 39*4882a593Smuzhiyun compatible = "simple-bus"; 40*4882a593Smuzhiyun ranges; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #address-cells = <1>; 43*4882a593Smuzhiyun #size-cells = <1>; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun apb { 46*4882a593Smuzhiyun compatible = "simple-bus"; 47*4882a593Smuzhiyun ranges; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #address-cells = <1>; 50*4882a593Smuzhiyun #size-cells = <1>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ehci0: ehci@1b000100 { 53*4882a593Smuzhiyun compatible = "generic-ehci"; 54*4882a593Smuzhiyun reg = <0x1b000100 0x100>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun status = "disabled"; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun uart0: uart@18020000 { 60*4882a593Smuzhiyun compatible = "ns16550"; 61*4882a593Smuzhiyun reg = <0x18020000 0x20>; 62*4882a593Smuzhiyun reg-shift = <2>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun status = "disabled"; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun gmac0: eth@0x19000000 { 68*4882a593Smuzhiyun compatible = "qca,ag934x-mac"; 69*4882a593Smuzhiyun reg = <0x19000000 0x200>; 70*4882a593Smuzhiyun phy = <&phy0>; 71*4882a593Smuzhiyun phy-mode = "rgmii"; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun status = "disabled"; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun mdio { 76*4882a593Smuzhiyun #address-cells = <1>; 77*4882a593Smuzhiyun #size-cells = <0>; 78*4882a593Smuzhiyun phy0: ethernet-phy@0 { 79*4882a593Smuzhiyun reg = <0>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun gmac1: eth@0x1a000000 { 85*4882a593Smuzhiyun compatible = "qca,ag934x-mac"; 86*4882a593Smuzhiyun reg = <0x1a000000 0x200>; 87*4882a593Smuzhiyun phy = <&phy1>; 88*4882a593Smuzhiyun phy-mode = "rgmii"; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun status = "disabled"; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun mdio { 93*4882a593Smuzhiyun #address-cells = <1>; 94*4882a593Smuzhiyun #size-cells = <0>; 95*4882a593Smuzhiyun phy1: ethernet-phy@0 { 96*4882a593Smuzhiyun reg = <0>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun spi0: spi@1f000000 { 103*4882a593Smuzhiyun compatible = "qca,ar7100-spi"; 104*4882a593Smuzhiyun reg = <0x1f000000 0x10>; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun status = "disabled"; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #address-cells = <1>; 109*4882a593Smuzhiyun #size-cells = <0>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun}; 113