1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * MIPS Coherence Manager (CM) Initialisation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2016 Imagination Technologies Ltd. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <asm/addrspace.h> 10*4882a593Smuzhiyun#include <asm/asm.h> 11*4882a593Smuzhiyun#include <asm/cm.h> 12*4882a593Smuzhiyun#include <asm/mipsregs.h> 13*4882a593Smuzhiyun#include <asm/regdef.h> 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunLEAF(mips_cm_map) 16*4882a593Smuzhiyun /* Config3 must exist for a CM to be present */ 17*4882a593Smuzhiyun mfc0 t0, CP0_CONFIG, 1 18*4882a593Smuzhiyun bgez t0, 2f 19*4882a593Smuzhiyun mfc0 t0, CP0_CONFIG, 2 20*4882a593Smuzhiyun bgez t0, 2f 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Check Config3.CMGCR to determine CM presence */ 23*4882a593Smuzhiyun mfc0 t0, CP0_CONFIG, 3 24*4882a593Smuzhiyun and t0, t0, MIPS_CONF3_CMGCR 25*4882a593Smuzhiyun beqz t0, 2f 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Find the current physical GCR base address */ 28*4882a593Smuzhiyun1: MFC0 t0, CP0_CMGCRBASE 29*4882a593Smuzhiyun PTR_SLL t0, t0, 4 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* If the GCRs are where we want, we're done */ 32*4882a593Smuzhiyun PTR_LI t1, CONFIG_MIPS_CM_BASE 33*4882a593Smuzhiyun beq t0, t1, 2f 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Move the GCRs to our configured base address */ 36*4882a593Smuzhiyun PTR_LI t2, CKSEG1 37*4882a593Smuzhiyun PTR_ADDU t0, t0, t2 38*4882a593Smuzhiyun sw zero, GCR_BASE_UPPER(t0) 39*4882a593Smuzhiyun sw t1, GCR_BASE(t0) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Re-check the GCR base */ 42*4882a593Smuzhiyun b 1b 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun2: jr ra 45*4882a593Smuzhiyun END(mips_cm_map) 46