1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013 - 2014 Xilinx, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_MICROBLAZE_SPL_H_ 10*4882a593Smuzhiyun #define _ASM_MICROBLAZE_SPL_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define BOOT_DEVICE_RAM 1 13*4882a593Smuzhiyun #define BOOT_DEVICE_NOR 2 14*4882a593Smuzhiyun #define BOOT_DEVICE_SPI 3 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #endif 17