1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/asm-microblaze/ptrace.h -- Access to CPU registers 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2003 John Williams <jwilliams@itee.uq.edu.au> 5*4882a593Smuzhiyun * Copyright (C) 2001,2002 NEC Corporation 6*4882a593Smuzhiyun * Copyright (C) 2001,2002 Miles Bader <miles@gnu.org> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General 9*4882a593Smuzhiyun * Public License. See the file COPYING in the main directory of this 10*4882a593Smuzhiyun * archive for more details. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Written by Miles Bader <miles@gnu.org> 13*4882a593Smuzhiyun * Microblaze port by John Williams 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __MICROBLAZE_PTRACE_H__ 17*4882a593Smuzhiyun #define __MICROBLAZE_PTRACE_H__ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Microblaze general purpose registers with special meanings. */ 21*4882a593Smuzhiyun #define GPR_ZERO 0 /* constant zero */ 22*4882a593Smuzhiyun #define GPR_ASM 18 /* reserved for assembler */ 23*4882a593Smuzhiyun #define GPR_SP 1 /* stack pointer */ 24*4882a593Smuzhiyun #define GPR_GP 2 /* global data pointer */ 25*4882a593Smuzhiyun #define GPR_EP 30 /* `element pointer' */ 26*4882a593Smuzhiyun #define GPR_LP 15 /* link pointer (current return address) */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* These aren't official names, but they make some code more descriptive. */ 29*4882a593Smuzhiyun #define GPR_ARG0 5 30*4882a593Smuzhiyun #define GPR_ARG1 6 31*4882a593Smuzhiyun #define GPR_ARG2 7 32*4882a593Smuzhiyun #define GPR_ARG3 8 33*4882a593Smuzhiyun #define GPR_ARG4 9 34*4882a593Smuzhiyun #define GPR_ARG5 10 35*4882a593Smuzhiyun #define GPR_RVAL0 3 36*4882a593Smuzhiyun #define GPR_RVAL1 4 37*4882a593Smuzhiyun #define GPR_RVAL GPR_RVAL0 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define NUM_GPRS 32 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* `system' registers. */ 42*4882a593Smuzhiyun /* Note these are old v850 values, microblaze has many fewer */ 43*4882a593Smuzhiyun #define SR_EIPC 0 44*4882a593Smuzhiyun #define SR_EIPSW 1 45*4882a593Smuzhiyun #define SR_FEPC 2 46*4882a593Smuzhiyun #define SR_FEPSW 3 47*4882a593Smuzhiyun #define SR_ECR 4 48*4882a593Smuzhiyun #define SR_PSW 5 49*4882a593Smuzhiyun #define SR_CTPC 16 50*4882a593Smuzhiyun #define SR_CTPSW 17 51*4882a593Smuzhiyun #define SR_DBPC 18 52*4882a593Smuzhiyun #define SR_DBPSW 19 53*4882a593Smuzhiyun #define SR_CTBP 20 54*4882a593Smuzhiyun #define SR_DIR 21 55*4882a593Smuzhiyun #define SR_ASID 23 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun typedef unsigned long microblaze_reg_t; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* How processor state is stored on the stack during a syscall/signal. 63*4882a593Smuzhiyun If you change this structure, change the associated assembly-language 64*4882a593Smuzhiyun macros below too (PT_*)! */ 65*4882a593Smuzhiyun struct pt_regs 66*4882a593Smuzhiyun { 67*4882a593Smuzhiyun /* General purpose registers. */ 68*4882a593Smuzhiyun microblaze_reg_t gpr[NUM_GPRS]; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun microblaze_reg_t pc; /* program counter */ 71*4882a593Smuzhiyun microblaze_reg_t psw; /* program status word */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun microblaze_reg_t kernel_mode; /* 1 if in `kernel mode', 0 if user mode */ 74*4882a593Smuzhiyun microblaze_reg_t single_step; /* 1 if in single step mode */ 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define instruction_pointer(regs) ((regs)->pc) 79*4882a593Smuzhiyun #define user_mode(regs) (!(regs)->kernel_mode) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* When a struct pt_regs is used to save user state for a system call in 82*4882a593Smuzhiyun the kernel, the system call is stored in the space for R0 (since it's 83*4882a593Smuzhiyun never used otherwise, R0 being a constant 0). Non-system-calls 84*4882a593Smuzhiyun simply store 0 there. */ 85*4882a593Smuzhiyun #define PT_REGS_SYSCALL(regs) (regs)->gpr[0] 86*4882a593Smuzhiyun #define PT_REGS_SET_SYSCALL(regs, val) ((regs)->gpr[0] = (val)) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* The number of bytes used to store each register. */ 92*4882a593Smuzhiyun #define _PT_REG_SIZE 4 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Offset of a general purpose register in a stuct pt_regs. */ 95*4882a593Smuzhiyun #define PT_GPR(num) ((num) * _PT_REG_SIZE) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* Offsets of various special registers & fields in a struct pt_regs. */ 98*4882a593Smuzhiyun #define NUM_SPECIAL 4 99*4882a593Smuzhiyun #define PT_PC ((NUM_GPRS + 0) * _PT_REG_SIZE) 100*4882a593Smuzhiyun #define PT_PSW ((NUM_GPRS + 1) * _PT_REG_SIZE) 101*4882a593Smuzhiyun #define PT_KERNEL_MODE ((NUM_GPRS + 2) * _PT_REG_SIZE) 102*4882a593Smuzhiyun #define PT_SINGLESTEP ((NUM_GPRS + 3) * _PT_REG_SIZE) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define PT_SYSCALL PT_GPR(0) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Size of struct pt_regs, including alignment. */ 107*4882a593Smuzhiyun #define PT_SIZE ((NUM_GPRS + NUM_SPECIAL) * _PT_REG_SIZE) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* These are `magic' values for PTRACE_PEEKUSR that return info about where 110*4882a593Smuzhiyun a process is located in memory. */ 111*4882a593Smuzhiyun #define PT_TEXT_ADDR (PT_SIZE + 1) 112*4882a593Smuzhiyun #define PT_TEXT_LEN (PT_SIZE + 2) 113*4882a593Smuzhiyun #define PT_DATA_ADDR (PT_SIZE + 3) 114*4882a593Smuzhiyun #define PT_DATA_LEN (PT_SIZE + 4) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #endif /* __MICROBLAZE_PTRACE_H__ */ 117