1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2011 The Chromium OS Authors. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MICROBLAZE_CACHE_H__ 8*4882a593Smuzhiyun #define __MICROBLAZE_CACHE_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * The microblaze can have either a 4 or 16 byte cacheline depending on whether 12*4882a593Smuzhiyun * you are using OPB(4) or CacheLink(16). If the board config has not specified 13*4882a593Smuzhiyun * a cacheline size we assume the larger value of 16 bytes for DMA buffer 14*4882a593Smuzhiyun * alignment. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #ifdef CONFIG_SYS_CACHELINE_SIZE 17*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 18*4882a593Smuzhiyun #else 19*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN 16 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif /* __MICROBLAZE_CACHE_H__ */ 23