1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007 Michal Simek 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Michal SIMEK <monstr@monstr.eu> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* FSL macros */ 10*4882a593Smuzhiyun #define NGET(val, fslnum) \ 11*4882a593Smuzhiyun __asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val)); 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define GET(val, fslnum) \ 14*4882a593Smuzhiyun __asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val)); 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define NCGET(val, fslnum) \ 17*4882a593Smuzhiyun __asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val)); 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CGET(val, fslnum) \ 20*4882a593Smuzhiyun __asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val)); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define NPUT(val, fslnum) \ 23*4882a593Smuzhiyun __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val)); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define PUT(val, fslnum) \ 26*4882a593Smuzhiyun __asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val)); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define NCPUT(val, fslnum) \ 29*4882a593Smuzhiyun __asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val)); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CPUT(val, fslnum) \ 32*4882a593Smuzhiyun __asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val)); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* CPU dependent */ 35*4882a593Smuzhiyun /* machine status register */ 36*4882a593Smuzhiyun #define MFS(val, reg) \ 37*4882a593Smuzhiyun __asm__ __volatile__ ("mfs %0," #reg :"=r" (val)); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define MTS(val, reg) \ 40*4882a593Smuzhiyun __asm__ __volatile__ ("mts " #reg ", %0"::"r" (val)); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* get return address from interrupt */ 43*4882a593Smuzhiyun #define R14(val) \ 44*4882a593Smuzhiyun __asm__ __volatile__ ("addi %0, r14, 0":"=r" (val)); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* get return address from interrupt */ 47*4882a593Smuzhiyun #define R17(val) \ 48*4882a593Smuzhiyun __asm__ __volatile__ ("addi %0, r17, 0" : "=r" (val)); 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define NOP __asm__ __volatile__ ("nop"); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* use machine status registe USE_MSR_REG */ 53*4882a593Smuzhiyun #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 1 54*4882a593Smuzhiyun #define MSRSET(val) \ 55*4882a593Smuzhiyun __asm__ __volatile__ ("msrset r0," #val ); 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define MSRCLR(val) \ 58*4882a593Smuzhiyun __asm__ __volatile__ ("msrclr r0," #val ); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #else 61*4882a593Smuzhiyun #define MSRSET(val) \ 62*4882a593Smuzhiyun { \ 63*4882a593Smuzhiyun register unsigned tmp; \ 64*4882a593Smuzhiyun __asm__ __volatile__ (" \ 65*4882a593Smuzhiyun mfs %0, rmsr; \ 66*4882a593Smuzhiyun ori %0, %0, "#val"; \ 67*4882a593Smuzhiyun mts rmsr, %0; \ 68*4882a593Smuzhiyun nop;" \ 69*4882a593Smuzhiyun : "=r" (tmp) \ 70*4882a593Smuzhiyun : "d" (val) \ 71*4882a593Smuzhiyun : "memory"); \ 72*4882a593Smuzhiyun } 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define MSRCLR(val) \ 75*4882a593Smuzhiyun { \ 76*4882a593Smuzhiyun register unsigned tmp; \ 77*4882a593Smuzhiyun __asm__ __volatile__ (" \ 78*4882a593Smuzhiyun mfs %0, rmsr; \ 79*4882a593Smuzhiyun andi %0, %0, ~"#val"; \ 80*4882a593Smuzhiyun mts rmsr, %0; \ 81*4882a593Smuzhiyun nop;" \ 82*4882a593Smuzhiyun : "=r" (tmp) \ 83*4882a593Smuzhiyun : "d" (val) \ 84*4882a593Smuzhiyun : "memory"); \ 85*4882a593Smuzhiyun } 86*4882a593Smuzhiyun #endif 87