1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Intel Quark MRC bindings include several properties 7*4882a593Smuzhiyun * as part of an Intel Quark MRC node. In most cases, 8*4882a593Smuzhiyun * the value of these properties uses the standard values 9*4882a593Smuzhiyun * defined in this header. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _DT_BINDINGS_QRK_MRC_H_ 13*4882a593Smuzhiyun #define _DT_BINDINGS_QRK_MRC_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* MRC platform data flags */ 16*4882a593Smuzhiyun #define MRC_FLAG_ECC_EN 0x00000001 17*4882a593Smuzhiyun #define MRC_FLAG_SCRAMBLE_EN 0x00000002 18*4882a593Smuzhiyun #define MRC_FLAG_MEMTEST_EN 0x00000004 19*4882a593Smuzhiyun /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ 20*4882a593Smuzhiyun #define MRC_FLAG_TOP_TREE_EN 0x00000008 21*4882a593Smuzhiyun /* If set ODR signal is asserted to DRAM devices on writes */ 22*4882a593Smuzhiyun #define MRC_FLAG_WR_ODT_EN 0x00000010 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* DRAM width */ 25*4882a593Smuzhiyun #define DRAM_WIDTH_X8 0 26*4882a593Smuzhiyun #define DRAM_WIDTH_X16 1 27*4882a593Smuzhiyun #define DRAM_WIDTH_X32 2 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* DRAM speed */ 30*4882a593Smuzhiyun #define DRAM_FREQ_800 0 31*4882a593Smuzhiyun #define DRAM_FREQ_1066 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* DRAM type */ 34*4882a593Smuzhiyun #define DRAM_TYPE_DDR3 0 35*4882a593Smuzhiyun #define DRAM_TYPE_DDR3L 1 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* DRAM rank mask */ 38*4882a593Smuzhiyun #define DRAM_RANK(n) (1 << (n)) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* DRAM channel mask */ 41*4882a593Smuzhiyun #define DRAM_CHANNEL(n) (1 << (n)) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* DRAM channel width */ 44*4882a593Smuzhiyun #define DRAM_CHANNEL_WIDTH_X8 0 45*4882a593Smuzhiyun #define DRAM_CHANNEL_WIDTH_X16 1 46*4882a593Smuzhiyun #define DRAM_CHANNEL_WIDTH_X32 2 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* DRAM address mode */ 49*4882a593Smuzhiyun #define DRAM_ADDR_MODE0 0 50*4882a593Smuzhiyun #define DRAM_ADDR_MODE1 1 51*4882a593Smuzhiyun #define DRAM_ADDR_MODE2 2 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* DRAM refresh rate */ 54*4882a593Smuzhiyun #define DRAM_REFRESH_RATE_195US 1 55*4882a593Smuzhiyun #define DRAM_REFRESH_RATE_39US 2 56*4882a593Smuzhiyun #define DRAM_REFRESH_RATE_785US 3 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* DRAM SR temprature range */ 59*4882a593Smuzhiyun #define DRAM_SRT_RANGE_NORMAL 0 60*4882a593Smuzhiyun #define DRAM_SRT_RANGE_EXTENDED 1 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* DRAM ron value */ 63*4882a593Smuzhiyun #define DRAM_RON_34OHM 0 64*4882a593Smuzhiyun #define DRAM_RON_40OHM 1 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* DRAM rtt nom value */ 67*4882a593Smuzhiyun #define DRAM_RTT_NOM_40OHM 0 68*4882a593Smuzhiyun #define DRAM_RTT_NOM_60OHM 1 69*4882a593Smuzhiyun #define DRAM_RTT_NOM_120OHM 2 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* DRAM rd odt value */ 72*4882a593Smuzhiyun #define DRAM_RD_ODT_OFF 0 73*4882a593Smuzhiyun #define DRAM_RD_ODT_60OHM 1 74*4882a593Smuzhiyun #define DRAM_RD_ODT_120OHM 2 75*4882a593Smuzhiyun #define DRAM_RD_ODT_180OHM 3 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* DRAM density */ 78*4882a593Smuzhiyun #define DRAM_DENSITY_512M 0 79*4882a593Smuzhiyun #define DRAM_DENSITY_1G 1 80*4882a593Smuzhiyun #define DRAM_DENSITY_2G 2 81*4882a593Smuzhiyun #define DRAM_DENSITY_4G 3 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif /* _DT_BINDINGS_QRK_MRC_H_ */ 84