1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra20-car. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 5*4882a593Smuzhiyun * registers. These IDs often match those in the CAR's RST_DEVICES registers, 6*4882a593Smuzhiyun * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 7*4882a593Smuzhiyun * this case, those clocks are assigned IDs above 95 in order to highlight 8*4882a593Smuzhiyun * this issue. Implementations that interpret these clock IDs as bit values 9*4882a593Smuzhiyun * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 10*4882a593Smuzhiyun * explicitly handle these special cases. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * The balance of the clocks controlled by the CAR are assigned IDs of 96 and 13*4882a593Smuzhiyun * above. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H 17*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define TEGRA20_CLK_CPU 0 20*4882a593Smuzhiyun /* 1 */ 21*4882a593Smuzhiyun /* 2 */ 22*4882a593Smuzhiyun #define TEGRA20_CLK_AC97 3 23*4882a593Smuzhiyun #define TEGRA20_CLK_RTC 4 24*4882a593Smuzhiyun #define TEGRA20_CLK_TIMER 5 25*4882a593Smuzhiyun #define TEGRA20_CLK_UARTA 6 26*4882a593Smuzhiyun /* 7 (register bit affects uart2 and vfir) */ 27*4882a593Smuzhiyun #define TEGRA20_CLK_GPIO 8 28*4882a593Smuzhiyun #define TEGRA20_CLK_SDMMC2 9 29*4882a593Smuzhiyun /* 10 (register bit affects spdif_in and spdif_out) */ 30*4882a593Smuzhiyun #define TEGRA20_CLK_I2S1 11 31*4882a593Smuzhiyun #define TEGRA20_CLK_I2C1 12 32*4882a593Smuzhiyun #define TEGRA20_CLK_NDFLASH 13 33*4882a593Smuzhiyun #define TEGRA20_CLK_SDMMC1 14 34*4882a593Smuzhiyun #define TEGRA20_CLK_SDMMC4 15 35*4882a593Smuzhiyun #define TEGRA20_CLK_TWC 16 36*4882a593Smuzhiyun #define TEGRA20_CLK_PWM 17 37*4882a593Smuzhiyun #define TEGRA20_CLK_I2S2 18 38*4882a593Smuzhiyun #define TEGRA20_CLK_EPP 19 39*4882a593Smuzhiyun /* 20 (register bit affects vi and vi_sensor) */ 40*4882a593Smuzhiyun #define TEGRA20_CLK_GR2D 21 41*4882a593Smuzhiyun #define TEGRA20_CLK_USBD 22 42*4882a593Smuzhiyun #define TEGRA20_CLK_ISP 23 43*4882a593Smuzhiyun #define TEGRA20_CLK_GR3D 24 44*4882a593Smuzhiyun #define TEGRA20_CLK_IDE 25 45*4882a593Smuzhiyun #define TEGRA20_CLK_DISP2 26 46*4882a593Smuzhiyun #define TEGRA20_CLK_DISP1 27 47*4882a593Smuzhiyun #define TEGRA20_CLK_HOST1X 28 48*4882a593Smuzhiyun #define TEGRA20_CLK_VCP 29 49*4882a593Smuzhiyun /* 30 */ 50*4882a593Smuzhiyun #define TEGRA20_CLK_CACHE2 31 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define TEGRA20_CLK_MC 32 53*4882a593Smuzhiyun #define TEGRA20_CLK_AHBDMA 33 54*4882a593Smuzhiyun #define TEGRA20_CLK_APBDMA 34 55*4882a593Smuzhiyun /* 35 */ 56*4882a593Smuzhiyun #define TEGRA20_CLK_KBC 36 57*4882a593Smuzhiyun #define TEGRA20_CLK_STAT_MON 37 58*4882a593Smuzhiyun #define TEGRA20_CLK_PMC 38 59*4882a593Smuzhiyun #define TEGRA20_CLK_FUSE 39 60*4882a593Smuzhiyun #define TEGRA20_CLK_KFUSE 40 61*4882a593Smuzhiyun #define TEGRA20_CLK_SBC1 41 62*4882a593Smuzhiyun #define TEGRA20_CLK_NOR 42 63*4882a593Smuzhiyun #define TEGRA20_CLK_SPI 43 64*4882a593Smuzhiyun #define TEGRA20_CLK_SBC2 44 65*4882a593Smuzhiyun #define TEGRA20_CLK_XIO 45 66*4882a593Smuzhiyun #define TEGRA20_CLK_SBC3 46 67*4882a593Smuzhiyun #define TEGRA20_CLK_DVC 47 68*4882a593Smuzhiyun #define TEGRA20_CLK_DSI 48 69*4882a593Smuzhiyun /* 49 (register bit affects tvo and cve) */ 70*4882a593Smuzhiyun #define TEGRA20_CLK_MIPI 50 71*4882a593Smuzhiyun #define TEGRA20_CLK_HDMI 51 72*4882a593Smuzhiyun #define TEGRA20_CLK_CSI 52 73*4882a593Smuzhiyun #define TEGRA20_CLK_TVDAC 53 74*4882a593Smuzhiyun #define TEGRA20_CLK_I2C2 54 75*4882a593Smuzhiyun #define TEGRA20_CLK_UARTC 55 76*4882a593Smuzhiyun /* 56 */ 77*4882a593Smuzhiyun #define TEGRA20_CLK_EMC 57 78*4882a593Smuzhiyun #define TEGRA20_CLK_USB2 58 79*4882a593Smuzhiyun #define TEGRA20_CLK_USB3 59 80*4882a593Smuzhiyun #define TEGRA20_CLK_MPE 60 81*4882a593Smuzhiyun #define TEGRA20_CLK_VDE 61 82*4882a593Smuzhiyun #define TEGRA20_CLK_BSEA 62 83*4882a593Smuzhiyun #define TEGRA20_CLK_BSEV 63 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define TEGRA20_CLK_SPEEDO 64 86*4882a593Smuzhiyun #define TEGRA20_CLK_UARTD 65 87*4882a593Smuzhiyun #define TEGRA20_CLK_UARTE 66 88*4882a593Smuzhiyun #define TEGRA20_CLK_I2C3 67 89*4882a593Smuzhiyun #define TEGRA20_CLK_SBC4 68 90*4882a593Smuzhiyun #define TEGRA20_CLK_SDMMC3 69 91*4882a593Smuzhiyun #define TEGRA20_CLK_PEX 70 92*4882a593Smuzhiyun #define TEGRA20_CLK_OWR 71 93*4882a593Smuzhiyun #define TEGRA20_CLK_AFI 72 94*4882a593Smuzhiyun #define TEGRA20_CLK_CSITE 73 95*4882a593Smuzhiyun /* 74 */ 96*4882a593Smuzhiyun #define TEGRA20_CLK_AVPUCQ 75 97*4882a593Smuzhiyun #define TEGRA20_CLK_LA 76 98*4882a593Smuzhiyun /* 77 */ 99*4882a593Smuzhiyun /* 78 */ 100*4882a593Smuzhiyun /* 79 */ 101*4882a593Smuzhiyun /* 80 */ 102*4882a593Smuzhiyun /* 81 */ 103*4882a593Smuzhiyun /* 82 */ 104*4882a593Smuzhiyun /* 83 */ 105*4882a593Smuzhiyun #define TEGRA20_CLK_IRAMA 84 106*4882a593Smuzhiyun #define TEGRA20_CLK_IRAMB 85 107*4882a593Smuzhiyun #define TEGRA20_CLK_IRAMC 86 108*4882a593Smuzhiyun #define TEGRA20_CLK_IRAMD 87 109*4882a593Smuzhiyun #define TEGRA20_CLK_CRAM2 88 110*4882a593Smuzhiyun #define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ 111*4882a593Smuzhiyun #define TEGRA20_CLK_CLK_D 90 112*4882a593Smuzhiyun /* 91 */ 113*4882a593Smuzhiyun #define TEGRA20_CLK_CSUS 92 114*4882a593Smuzhiyun #define TEGRA20_CLK_CDEV2 93 115*4882a593Smuzhiyun #define TEGRA20_CLK_CDEV1 94 116*4882a593Smuzhiyun /* 95 */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define TEGRA20_CLK_UARTB 96 119*4882a593Smuzhiyun #define TEGRA20_CLK_VFIR 97 120*4882a593Smuzhiyun #define TEGRA20_CLK_SPDIF_IN 98 121*4882a593Smuzhiyun #define TEGRA20_CLK_SPDIF_OUT 99 122*4882a593Smuzhiyun #define TEGRA20_CLK_VI 100 123*4882a593Smuzhiyun #define TEGRA20_CLK_VI_SENSOR 101 124*4882a593Smuzhiyun #define TEGRA20_CLK_TVO 102 125*4882a593Smuzhiyun #define TEGRA20_CLK_CVE 103 126*4882a593Smuzhiyun #define TEGRA20_CLK_OSC 104 127*4882a593Smuzhiyun #define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ 128*4882a593Smuzhiyun #define TEGRA20_CLK_CLK_M 106 129*4882a593Smuzhiyun #define TEGRA20_CLK_SCLK 107 130*4882a593Smuzhiyun #define TEGRA20_CLK_CCLK 108 131*4882a593Smuzhiyun #define TEGRA20_CLK_HCLK 109 132*4882a593Smuzhiyun #define TEGRA20_CLK_PCLK 110 133*4882a593Smuzhiyun #define TEGRA20_CLK_BLINK 111 134*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_A 112 135*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_A_OUT0 113 136*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_C 114 137*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_C_OUT1 115 138*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_D 116 139*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_D_OUT0 117 140*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_E 118 141*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_M 119 142*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_M_OUT1 120 143*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_P 121 144*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_P_OUT1 122 145*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_P_OUT2 123 146*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_P_OUT3 124 147*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_P_OUT4 125 148*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_S 126 149*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_U 127 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_X 128 152*4882a593Smuzhiyun #define TEGRA20_CLK_COP 129 /* a/k/a avp */ 153*4882a593Smuzhiyun #define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ 154*4882a593Smuzhiyun #define TEGRA20_CLK_PLL_REF 131 155*4882a593Smuzhiyun #define TEGRA20_CLK_TWD 132 156*4882a593Smuzhiyun #define TEGRA20_CLK_CLK_MAX 133 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */ 159