1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * stm32fx-clock.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2016 STMicroelectronics 5*4882a593Smuzhiyun * Author: Gabriel Fernandez for STMicroelectronics. 6*4882a593Smuzhiyun * License terms: GNU General Public License (GPL), version 2 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * List of clocks wich are not derived from system clock (SYSCLOCK) 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * The index of these clocks is the secondary index of DT bindings 13*4882a593Smuzhiyun * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt) 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * e.g: 16*4882a593Smuzhiyun <assigned-clocks = <&rcc 1 CLK_LSE>; 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_STMFX_H 20*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_STMFX_H 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define SYSTICK 0 23*4882a593Smuzhiyun #define FCLK 1 24*4882a593Smuzhiyun #define CLK_LSI 2 25*4882a593Smuzhiyun #define CLK_LSE 3 26*4882a593Smuzhiyun #define CLK_HSE_RTC 4 27*4882a593Smuzhiyun #define CLK_RTC 5 28*4882a593Smuzhiyun #define PLL_VCO_I2S 6 29*4882a593Smuzhiyun #define PLL_VCO_SAI 7 30*4882a593Smuzhiyun #define CLK_LCD 8 31*4882a593Smuzhiyun #define CLK_I2S 9 32*4882a593Smuzhiyun #define CLK_SAI1 10 33*4882a593Smuzhiyun #define CLK_SAI2 11 34*4882a593Smuzhiyun #define CLK_I2SQ_PDIV 12 35*4882a593Smuzhiyun #define CLK_SAIQ_PDIV 13 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define END_PRIMARY_CLK 14 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CLK_HSI 14 40*4882a593Smuzhiyun #define CLK_SYSCLK 15 41*4882a593Smuzhiyun #define CLK_HDMI_CEC 16 42*4882a593Smuzhiyun #define CLK_SPDIF 17 43*4882a593Smuzhiyun #define CLK_USART1 18 44*4882a593Smuzhiyun #define CLK_USART2 19 45*4882a593Smuzhiyun #define CLK_USART3 20 46*4882a593Smuzhiyun #define CLK_UART4 21 47*4882a593Smuzhiyun #define CLK_UART5 22 48*4882a593Smuzhiyun #define CLK_USART6 23 49*4882a593Smuzhiyun #define CLK_UART7 24 50*4882a593Smuzhiyun #define CLK_UART8 25 51*4882a593Smuzhiyun #define CLK_I2C1 26 52*4882a593Smuzhiyun #define CLK_I2C2 27 53*4882a593Smuzhiyun #define CLK_I2C3 28 54*4882a593Smuzhiyun #define CLK_I2C4 29 55*4882a593Smuzhiyun #define CLK_LPTIMER 30 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define END_PRIMARY_CLK_F7 31 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif 60