1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2016 Google Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* Core Clocks */ 8*4882a593Smuzhiyun #define PLL_HPLL 1 9*4882a593Smuzhiyun #define PLL_DPLL 2 10*4882a593Smuzhiyun #define PLL_D2PLL 3 11*4882a593Smuzhiyun #define PLL_MPLL 4 12*4882a593Smuzhiyun #define ARMCLK 5 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Bus Clocks, derived from core clocks */ 16*4882a593Smuzhiyun #define BCLK_PCLK 101 17*4882a593Smuzhiyun #define BCLK_LHCLK 102 18*4882a593Smuzhiyun #define BCLK_MACCLK 103 19*4882a593Smuzhiyun #define BCLK_SDCLK 104 20*4882a593Smuzhiyun #define BCLK_ARMCLK 105 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define MCLK_DDR 201 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Special clocks */ 25*4882a593Smuzhiyun #define PCLK_UART1 501 26*4882a593Smuzhiyun #define PCLK_UART2 502 27*4882a593Smuzhiyun #define PCLK_UART3 503 28*4882a593Smuzhiyun #define PCLK_UART4 504 29*4882a593Smuzhiyun #define PCLK_UART5 505 30*4882a593Smuzhiyun #define PCLK_MAC1 506 31*4882a593Smuzhiyun #define PCLK_MAC2 507 32