1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007 Michal Simek
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Michal SIMEK <monstr@monstr.eu>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/asm.h>
11*4882a593Smuzhiyun
dcache_status(void)12*4882a593Smuzhiyun int dcache_status (void)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun int i = 0;
15*4882a593Smuzhiyun int mask = 0x80;
16*4882a593Smuzhiyun __asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
17*4882a593Smuzhiyun /* i&=0x80 */
18*4882a593Smuzhiyun __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
19*4882a593Smuzhiyun return i;
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun
icache_status(void)22*4882a593Smuzhiyun int icache_status (void)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun int i = 0;
25*4882a593Smuzhiyun int mask = 0x20;
26*4882a593Smuzhiyun __asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
27*4882a593Smuzhiyun /* i&=0x20 */
28*4882a593Smuzhiyun __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
29*4882a593Smuzhiyun return i;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
icache_enable(void)32*4882a593Smuzhiyun void icache_enable (void) {
33*4882a593Smuzhiyun MSRSET(0x20);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
icache_disable(void)36*4882a593Smuzhiyun void icache_disable(void) {
37*4882a593Smuzhiyun /* we are not generate ICACHE size -> flush whole cache */
38*4882a593Smuzhiyun flush_cache(0, 32768);
39*4882a593Smuzhiyun MSRCLR(0x20);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
dcache_enable(void)42*4882a593Smuzhiyun void dcache_enable (void) {
43*4882a593Smuzhiyun MSRSET(0x80);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
dcache_disable(void)46*4882a593Smuzhiyun void dcache_disable(void) {
47*4882a593Smuzhiyun #ifdef XILINX_USE_DCACHE
48*4882a593Smuzhiyun flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
49*4882a593Smuzhiyun #endif
50*4882a593Smuzhiyun MSRCLR(0x80);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
flush_cache(ulong addr,ulong size)53*4882a593Smuzhiyun void flush_cache (ulong addr, ulong size)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun int i;
56*4882a593Smuzhiyun for (i = 0; i < size; i += 4)
57*4882a593Smuzhiyun asm volatile (
58*4882a593Smuzhiyun #ifdef CONFIG_ICACHE
59*4882a593Smuzhiyun "wic %0, r0;"
60*4882a593Smuzhiyun #endif
61*4882a593Smuzhiyun "nop;"
62*4882a593Smuzhiyun #ifdef CONFIG_DCACHE
63*4882a593Smuzhiyun "wdc.flush %0, r0;"
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun "nop;"
66*4882a593Smuzhiyun :
67*4882a593Smuzhiyun : "r" (addr + i)
68*4882a593Smuzhiyun : "memory");
69*4882a593Smuzhiyun }
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