1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * timer.h -- ColdFire internal TIMER support defines. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /****************************************************************************/ 11*4882a593Smuzhiyun #ifndef timer_h 12*4882a593Smuzhiyun #define timer_h 13*4882a593Smuzhiyun /****************************************************************************/ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /****************************************************************************/ 16*4882a593Smuzhiyun /* Timer structure */ 17*4882a593Smuzhiyun /****************************************************************************/ 18*4882a593Smuzhiyun /* DMA Timer module registers */ 19*4882a593Smuzhiyun typedef struct dtimer_ctrl { 20*4882a593Smuzhiyun #if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ 21*4882a593Smuzhiyun defined(CONFIG_M5272) || defined(CONFIG_M5307) 22*4882a593Smuzhiyun u16 tmr; /* 0x00 Mode register */ 23*4882a593Smuzhiyun u16 res1; /* 0x02 */ 24*4882a593Smuzhiyun u16 trr; /* 0x04 Reference register */ 25*4882a593Smuzhiyun u16 res2; /* 0x06 */ 26*4882a593Smuzhiyun u16 tcr; /* 0x08 Capture register */ 27*4882a593Smuzhiyun u16 res3; /* 0x0A */ 28*4882a593Smuzhiyun u16 tcn; /* 0x0C Counter register */ 29*4882a593Smuzhiyun u16 res4; /* 0x0E */ 30*4882a593Smuzhiyun u8 res6; /* 0x10 */ 31*4882a593Smuzhiyun u8 ter; /* 0x11 Event register */ 32*4882a593Smuzhiyun u16 res7; /* 0x12 */ 33*4882a593Smuzhiyun #else 34*4882a593Smuzhiyun u16 tmr; /* 0x00 Mode register */ 35*4882a593Smuzhiyun u8 txmr; /* 0x02 Extended Mode register */ 36*4882a593Smuzhiyun u8 ter; /* 0x03 Event register */ 37*4882a593Smuzhiyun u32 trr; /* 0x04 Reference register */ 38*4882a593Smuzhiyun u32 tcr; /* 0x08 Capture register */ 39*4882a593Smuzhiyun u32 tcn; /* 0x0C Counter register */ 40*4882a593Smuzhiyun #endif 41*4882a593Smuzhiyun } dtmr_t; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /*Programmable Interrupt Timer */ 44*4882a593Smuzhiyun typedef struct pit_ctrl { 45*4882a593Smuzhiyun u16 pcsr; /* 0x00 Control and Status Register */ 46*4882a593Smuzhiyun u16 pmr; /* 0x02 Modulus Register */ 47*4882a593Smuzhiyun u16 pcntr; /* 0x04 Count Register */ 48*4882a593Smuzhiyun } pit_t; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /********************************************************************* 51*4882a593Smuzhiyun * DMA Timers (DTIM) 52*4882a593Smuzhiyun *********************************************************************/ 53*4882a593Smuzhiyun /* Bit definitions and macros for DTMR */ 54*4882a593Smuzhiyun #define DTIM_DTMR_RST (0x0001) /* Reset */ 55*4882a593Smuzhiyun #define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ 56*4882a593Smuzhiyun #define DTIM_DTMR_FRR (0x0008) /* Free run/restart */ 57*4882a593Smuzhiyun #define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */ 58*4882a593Smuzhiyun #define DTIM_DTMR_OM (0x0020) /* Output Mode */ 59*4882a593Smuzhiyun #define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ 60*4882a593Smuzhiyun #define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ 61*4882a593Smuzhiyun #define DTIM_DTMR_RST_EN (0x0001) 62*4882a593Smuzhiyun #define DTIM_DTMR_RST_RST (0x0000) 63*4882a593Smuzhiyun #define DTIM_DTMR_CE_ANY (0x00C0) 64*4882a593Smuzhiyun #define DTIM_DTMR_CE_FALL (0x0080) 65*4882a593Smuzhiyun #define DTIM_DTMR_CE_RISE (0x0040) 66*4882a593Smuzhiyun #define DTIM_DTMR_CE_NONE (0x0000) 67*4882a593Smuzhiyun #define DTIM_DTMR_CLK_DTIN (0x0006) 68*4882a593Smuzhiyun #define DTIM_DTMR_CLK_DIV16 (0x0004) 69*4882a593Smuzhiyun #define DTIM_DTMR_CLK_DIV1 (0x0002) 70*4882a593Smuzhiyun #define DTIM_DTMR_CLK_STOP (0x0000) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Bit definitions and macros for DTXMR */ 73*4882a593Smuzhiyun #define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ 74*4882a593Smuzhiyun #define DTIM_DTXMR_DMAEN (0x80) /* DMA request */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Bit definitions and macros for DTER */ 77*4882a593Smuzhiyun #define DTIM_DTER_CAP (0x01) /* Capture event */ 78*4882a593Smuzhiyun #define DTIM_DTER_REF (0x02) /* Output reference event */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /********************************************************************* 81*4882a593Smuzhiyun * 82*4882a593Smuzhiyun * Programmable Interrupt Timer Modules (PIT) 83*4882a593Smuzhiyun * 84*4882a593Smuzhiyun *********************************************************************/ 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Bit definitions and macros for PCSR */ 87*4882a593Smuzhiyun #define PIT_PCSR_EN (0x0001) 88*4882a593Smuzhiyun #define PIT_PCSR_RLD (0x0002) 89*4882a593Smuzhiyun #define PIT_PCSR_PIF (0x0004) 90*4882a593Smuzhiyun #define PIT_PCSR_PIE (0x0008) 91*4882a593Smuzhiyun #define PIT_PCSR_OVW (0x0010) 92*4882a593Smuzhiyun #define PIT_PCSR_HALTED (0x0020) 93*4882a593Smuzhiyun #define PIT_PCSR_DOZE (0x0040) 94*4882a593Smuzhiyun #define PIT_PCSR_PRE(x) (((x)&0x000F)<<8) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* Bit definitions and macros for PMR */ 97*4882a593Smuzhiyun #define PIT_PMR_PM(x) (x) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* Bit definitions and macros for PCNTR */ 100*4882a593Smuzhiyun #define PIT_PCNTR_PC(x) (x) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /****************************************************************************/ 103*4882a593Smuzhiyun #endif /* timer_h */ 104