1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * RealTime Clock 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MCFRTC_H__ 11*4882a593Smuzhiyun #define __MCFRTC_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Real time Clock */ 14*4882a593Smuzhiyun typedef struct rtc_ctrl { 15*4882a593Smuzhiyun u32 hourmin; /* 0x00 Hours and Minutes Counter Register */ 16*4882a593Smuzhiyun u32 seconds; /* 0x04 Seconds Counter Register */ 17*4882a593Smuzhiyun u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */ 18*4882a593Smuzhiyun u32 alrm_sec; /* 0x0C Seconds Alarm Register */ 19*4882a593Smuzhiyun u32 cr; /* 0x10 Control Register */ 20*4882a593Smuzhiyun u32 isr; /* 0x14 Interrupt Status Register */ 21*4882a593Smuzhiyun u32 ier; /* 0x18 Interrupt Enable Register */ 22*4882a593Smuzhiyun u32 stpwatch; /* 0x1C Stopwatch Minutes Register */ 23*4882a593Smuzhiyun u32 days; /* 0x20 Days Counter Register */ 24*4882a593Smuzhiyun u32 alrm_day; /* 0x24 Days Alarm Register */ 25*4882a593Smuzhiyun void *extended; 26*4882a593Smuzhiyun } rtc_t; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Bit definitions and macros for HOURMIN */ 29*4882a593Smuzhiyun #define RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)) 30*4882a593Smuzhiyun #define RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Bit definitions and macros for SECONDS */ 33*4882a593Smuzhiyun #define RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Bit definitions and macros for ALRM_HM */ 36*4882a593Smuzhiyun #define RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)) 37*4882a593Smuzhiyun #define RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Bit definitions and macros for ALRM_SEC */ 40*4882a593Smuzhiyun #define RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Bit definitions and macros for CR */ 43*4882a593Smuzhiyun #define RTC_CR_SWR (0x00000001) 44*4882a593Smuzhiyun #define RTC_CR_XTL(x) (((x)&0x00000003)<<5) 45*4882a593Smuzhiyun #define RTC_CR_EN (0x00000080) 46*4882a593Smuzhiyun #define RTC_CR_32768 (0x0) 47*4882a593Smuzhiyun #define RTC_CR_32000 (0x1) 48*4882a593Smuzhiyun #define RTC_CR_38400 (0x2) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Bit definitions and macros for ISR */ 51*4882a593Smuzhiyun #define RTC_ISR_SW (0x00000001) 52*4882a593Smuzhiyun #define RTC_ISR_MIN (0x00000002) 53*4882a593Smuzhiyun #define RTC_ISR_ALM (0x00000004) 54*4882a593Smuzhiyun #define RTC_ISR_DAY (0x00000008) 55*4882a593Smuzhiyun #define RTC_ISR_1HZ (0x00000010) 56*4882a593Smuzhiyun #define RTC_ISR_HR (0x00000020) 57*4882a593Smuzhiyun #define RTC_ISR_2HZ (0x00000080) 58*4882a593Smuzhiyun #define RTC_ISR_SAM0 (0x00000100) 59*4882a593Smuzhiyun #define RTC_ISR_SAM1 (0x00000200) 60*4882a593Smuzhiyun #define RTC_ISR_SAM2 (0x00000400) 61*4882a593Smuzhiyun #define RTC_ISR_SAM3 (0x00000800) 62*4882a593Smuzhiyun #define RTC_ISR_SAM4 (0x00001000) 63*4882a593Smuzhiyun #define RTC_ISR_SAM5 (0x00002000) 64*4882a593Smuzhiyun #define RTC_ISR_SAM6 (0x00004000) 65*4882a593Smuzhiyun #define RTC_ISR_SAM7 (0x00008000) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Bit definitions and macros for IER */ 68*4882a593Smuzhiyun #define RTC_IER_SW (0x00000001) 69*4882a593Smuzhiyun #define RTC_IER_MIN (0x00000002) 70*4882a593Smuzhiyun #define RTC_IER_ALM (0x00000004) 71*4882a593Smuzhiyun #define RTC_IER_DAY (0x00000008) 72*4882a593Smuzhiyun #define RTC_IER_1HZ (0x00000010) 73*4882a593Smuzhiyun #define RTC_IER_HR (0x00000020) 74*4882a593Smuzhiyun #define RTC_IER_2HZ (0x00000080) 75*4882a593Smuzhiyun #define RTC_IER_SAM0 (0x00000100) 76*4882a593Smuzhiyun #define RTC_IER_SAM1 (0x00000200) 77*4882a593Smuzhiyun #define RTC_IER_SAM2 (0x00000400) 78*4882a593Smuzhiyun #define RTC_IER_SAM3 (0x00000800) 79*4882a593Smuzhiyun #define RTC_IER_SAM4 (0x00001000) 80*4882a593Smuzhiyun #define RTC_IER_SAM5 (0x00002000) 81*4882a593Smuzhiyun #define RTC_IER_SAM6 (0x00004000) 82*4882a593Smuzhiyun #define RTC_IER_SAM7 (0x00008000) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Bit definitions and macros for STPWCH */ 85*4882a593Smuzhiyun #define RTC_STPWCH_CNT(x) (((x)&0x0000003F)) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Bit definitions and macros for DAYS */ 88*4882a593Smuzhiyun #define RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Bit definitions and macros for ALRM_DAY */ 91*4882a593Smuzhiyun #define RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* __MCFRTC_H__ */ 94