1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * MCF5445x Internal Memory Map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MCF5445X__ 11*4882a593Smuzhiyun #define __MCF5445X__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /********************************************************************* 14*4882a593Smuzhiyun * Interrupt Controller (INTC) 15*4882a593Smuzhiyun *********************************************************************/ 16*4882a593Smuzhiyun #define INT0_LO_RSVD0 (0) 17*4882a593Smuzhiyun #define INT0_LO_EPORT1 (1) 18*4882a593Smuzhiyun #define INT0_LO_EPORT2 (2) 19*4882a593Smuzhiyun #define INT0_LO_EPORT3 (3) 20*4882a593Smuzhiyun #define INT0_LO_EPORT4 (4) 21*4882a593Smuzhiyun #define INT0_LO_EPORT5 (5) 22*4882a593Smuzhiyun #define INT0_LO_EPORT6 (6) 23*4882a593Smuzhiyun #define INT0_LO_EPORT7 (7) 24*4882a593Smuzhiyun #define INT0_LO_EDMA_00 (8) 25*4882a593Smuzhiyun #define INT0_LO_EDMA_01 (9) 26*4882a593Smuzhiyun #define INT0_LO_EDMA_02 (10) 27*4882a593Smuzhiyun #define INT0_LO_EDMA_03 (11) 28*4882a593Smuzhiyun #define INT0_LO_EDMA_04 (12) 29*4882a593Smuzhiyun #define INT0_LO_EDMA_05 (13) 30*4882a593Smuzhiyun #define INT0_LO_EDMA_06 (14) 31*4882a593Smuzhiyun #define INT0_LO_EDMA_07 (15) 32*4882a593Smuzhiyun #define INT0_LO_EDMA_08 (16) 33*4882a593Smuzhiyun #define INT0_LO_EDMA_09 (17) 34*4882a593Smuzhiyun #define INT0_LO_EDMA_10 (18) 35*4882a593Smuzhiyun #define INT0_LO_EDMA_11 (19) 36*4882a593Smuzhiyun #define INT0_LO_EDMA_12 (20) 37*4882a593Smuzhiyun #define INT0_LO_EDMA_13 (21) 38*4882a593Smuzhiyun #define INT0_LO_EDMA_14 (22) 39*4882a593Smuzhiyun #define INT0_LO_EDMA_15 (23) 40*4882a593Smuzhiyun #define INT0_LO_EDMA_ERR (24) 41*4882a593Smuzhiyun #define INT0_LO_SCM (25) 42*4882a593Smuzhiyun #define INT0_LO_UART0 (26) 43*4882a593Smuzhiyun #define INT0_LO_UART1 (27) 44*4882a593Smuzhiyun #define INT0_LO_UART2 (28) 45*4882a593Smuzhiyun #define INT0_LO_RSVD1 (29) 46*4882a593Smuzhiyun #define INT0_LO_I2C (30) 47*4882a593Smuzhiyun #define INT0_LO_QSPI (31) 48*4882a593Smuzhiyun #define INT0_HI_DTMR0 (32) 49*4882a593Smuzhiyun #define INT0_HI_DTMR1 (33) 50*4882a593Smuzhiyun #define INT0_HI_DTMR2 (34) 51*4882a593Smuzhiyun #define INT0_HI_DTMR3 (35) 52*4882a593Smuzhiyun #define INT0_HI_FEC0_TXF (36) 53*4882a593Smuzhiyun #define INT0_HI_FEC0_TXB (37) 54*4882a593Smuzhiyun #define INT0_HI_FEC0_UN (38) 55*4882a593Smuzhiyun #define INT0_HI_FEC0_RL (39) 56*4882a593Smuzhiyun #define INT0_HI_FEC0_RXF (40) 57*4882a593Smuzhiyun #define INT0_HI_FEC0_RXB (41) 58*4882a593Smuzhiyun #define INT0_HI_FEC0_MII (42) 59*4882a593Smuzhiyun #define INT0_HI_FEC0_LC (43) 60*4882a593Smuzhiyun #define INT0_HI_FEC0_HBERR (44) 61*4882a593Smuzhiyun #define INT0_HI_FEC0_GRA (45) 62*4882a593Smuzhiyun #define INT0_HI_FEC0_EBERR (46) 63*4882a593Smuzhiyun #define INT0_HI_FEC0_BABT (47) 64*4882a593Smuzhiyun #define INT0_HI_FEC0_BABR (48) 65*4882a593Smuzhiyun #define INT0_HI_FEC1_TXF (49) 66*4882a593Smuzhiyun #define INT0_HI_FEC1_TXB (50) 67*4882a593Smuzhiyun #define INT0_HI_FEC1_UN (51) 68*4882a593Smuzhiyun #define INT0_HI_FEC1_RL (52) 69*4882a593Smuzhiyun #define INT0_HI_FEC1_RXF (53) 70*4882a593Smuzhiyun #define INT0_HI_FEC1_RXB (54) 71*4882a593Smuzhiyun #define INT0_HI_FEC1_MII (55) 72*4882a593Smuzhiyun #define INT0_HI_FEC1_LC (56) 73*4882a593Smuzhiyun #define INT0_HI_FEC1_HBERR (57) 74*4882a593Smuzhiyun #define INT0_HI_FEC1_GRA (58) 75*4882a593Smuzhiyun #define INT0_HI_FEC1_EBERR (59) 76*4882a593Smuzhiyun #define INT0_HI_FEC1_BABT (60) 77*4882a593Smuzhiyun #define INT0_HI_FEC1_BABR (61) 78*4882a593Smuzhiyun #define INT0_HI_SCMIR (62) 79*4882a593Smuzhiyun #define INT0_HI_RTC_ISR (63) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define INT1_HI_DSPI_EOQF (33) 82*4882a593Smuzhiyun #define INT1_HI_DSPI_TFFF (34) 83*4882a593Smuzhiyun #define INT1_HI_DSPI_TCF (35) 84*4882a593Smuzhiyun #define INT1_HI_DSPI_TFUF (36) 85*4882a593Smuzhiyun #define INT1_HI_DSPI_RFDF (37) 86*4882a593Smuzhiyun #define INT1_HI_DSPI_RFOF (38) 87*4882a593Smuzhiyun #define INT1_HI_DSPI_RFOF_TFUF (39) 88*4882a593Smuzhiyun #define INT1_HI_RNG_EI (40) 89*4882a593Smuzhiyun #define INT1_HI_PIT0_PIF (43) 90*4882a593Smuzhiyun #define INT1_HI_PIT1_PIF (44) 91*4882a593Smuzhiyun #define INT1_HI_PIT2_PIF (45) 92*4882a593Smuzhiyun #define INT1_HI_PIT3_PIF (46) 93*4882a593Smuzhiyun #define INT1_HI_USBOTG_USBSTS (47) 94*4882a593Smuzhiyun #define INT1_HI_SSI_ISR (49) 95*4882a593Smuzhiyun #define INT1_HI_CCM_UOCSR (53) 96*4882a593Smuzhiyun #define INT1_HI_ATA_ISR (54) 97*4882a593Smuzhiyun #define INT1_HI_PCI_SCR (55) 98*4882a593Smuzhiyun #define INT1_HI_PCI_ASR (56) 99*4882a593Smuzhiyun #define INT1_HI_PLL_LOCKS (57) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /********************************************************************* 102*4882a593Smuzhiyun * Watchdog Timer Modules (WTM) 103*4882a593Smuzhiyun *********************************************************************/ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Bit definitions and macros for WCR */ 106*4882a593Smuzhiyun #define WTM_WCR_EN (0x0001) 107*4882a593Smuzhiyun #define WTM_WCR_HALTED (0x0002) 108*4882a593Smuzhiyun #define WTM_WCR_DOZE (0x0004) 109*4882a593Smuzhiyun #define WTM_WCR_WAIT (0x0008) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /********************************************************************* 112*4882a593Smuzhiyun * Serial Boot Facility (SBF) 113*4882a593Smuzhiyun *********************************************************************/ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* Bit definitions and macros for SBFCR */ 116*4882a593Smuzhiyun #define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ 117*4882a593Smuzhiyun #define SBF_SBFCR_FR (0x0010) /* Fast read */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /********************************************************************* 120*4882a593Smuzhiyun * Reset Controller Module (RCM) 121*4882a593Smuzhiyun *********************************************************************/ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* Bit definitions and macros for RCR */ 124*4882a593Smuzhiyun #define RCM_RCR_FRCRSTOUT (0x40) 125*4882a593Smuzhiyun #define RCM_RCR_SOFTRST (0x80) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* Bit definitions and macros for RSR */ 128*4882a593Smuzhiyun #define RCM_RSR_LOL (0x01) 129*4882a593Smuzhiyun #define RCM_RSR_WDR_CORE (0x02) 130*4882a593Smuzhiyun #define RCM_RSR_EXT (0x04) 131*4882a593Smuzhiyun #define RCM_RSR_POR (0x08) 132*4882a593Smuzhiyun #define RCM_RSR_SOFT (0x20) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /********************************************************************* 135*4882a593Smuzhiyun * Chip Configuration Module (CCM) 136*4882a593Smuzhiyun *********************************************************************/ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* Bit definitions and macros for CCR_360 */ 139*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ 140*4882a593Smuzhiyun #define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ 141*4882a593Smuzhiyun #define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ 142*4882a593Smuzhiyun #define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ 143*4882a593Smuzhiyun #define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ 144*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ 145*4882a593Smuzhiyun #define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ 146*4882a593Smuzhiyun #define CCM_CCR_360_FBCONFIG_MASK (0x00E0) 147*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT2_MASK (0x0003) 148*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT3_MASK (0x0007) 149*4882a593Smuzhiyun #define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) 150*4882a593Smuzhiyun #define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) 151*4882a593Smuzhiyun #define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) 152*4882a593Smuzhiyun #define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) 153*4882a593Smuzhiyun #define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) 154*4882a593Smuzhiyun #define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) 155*4882a593Smuzhiyun #define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) 156*4882a593Smuzhiyun #define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) 157*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT2_12X (0x0000) 158*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT2_6X (0x0001) 159*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT2_16X (0x0002) 160*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT2_8X (0x0003) 161*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT3_20X (0x0000) 162*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT3_10X (0x0001) 163*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT3_24X (0x0002) 164*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT3_18X (0x0003) 165*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT3_12X (0x0004) 166*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT3_6X (0x0005) 167*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT3_16X (0x0006) 168*4882a593Smuzhiyun #define CCM_CCR_360_PLLMULT3_8X (0x0007) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* Bit definitions and macros for CCR_256 */ 171*4882a593Smuzhiyun #define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ 172*4882a593Smuzhiyun #define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */ 173*4882a593Smuzhiyun #define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ 174*4882a593Smuzhiyun #define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ 175*4882a593Smuzhiyun #define CCM_CCR_256_FBCONFIG_MASK (0x00E0) 176*4882a593Smuzhiyun #define CCM_CCR_256_FBCONFIG_NM_32 (0x0000) 177*4882a593Smuzhiyun #define CCM_CCR_256_FBCONFIG_NM_8 (0x0020) 178*4882a593Smuzhiyun #define CCM_CCR_256_FBCONFIG_NM_16 (0x0040) 179*4882a593Smuzhiyun #define CCM_CCR_256_FBCONFIG_M_32 (0x0080) 180*4882a593Smuzhiyun #define CCM_CCR_256_FBCONFIG_M_8 (0x00A0) 181*4882a593Smuzhiyun #define CCM_CCR_256_FBCONFIG_M_16 (0x00C0) 182*4882a593Smuzhiyun #define CCM_CCR_256_PLLMULT3_MASK (0x0007) 183*4882a593Smuzhiyun #define CCM_CCR_256_PLLMULT3_20X (0x0000) 184*4882a593Smuzhiyun #define CCM_CCR_256_PLLMULT3_10X (0x0001) 185*4882a593Smuzhiyun #define CCM_CCR_256_PLLMULT3_24X (0x0002) 186*4882a593Smuzhiyun #define CCM_CCR_256_PLLMULT3_18X (0x0003) 187*4882a593Smuzhiyun #define CCM_CCR_256_PLLMULT3_12X (0x0004) 188*4882a593Smuzhiyun #define CCM_CCR_256_PLLMULT3_6X (0x0005) 189*4882a593Smuzhiyun #define CCM_CCR_256_PLLMULT3_16X (0x0006) 190*4882a593Smuzhiyun #define CCM_CCR_256_PLLMULT3_8X (0x0007) 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* Bit definitions and macros for RCON_360 */ 193*4882a593Smuzhiyun #define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ 194*4882a593Smuzhiyun #define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ 195*4882a593Smuzhiyun #define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ 196*4882a593Smuzhiyun #define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ 197*4882a593Smuzhiyun #define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* Bit definitions and macros for RCON_256 */ 200*4882a593Smuzhiyun #define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ 201*4882a593Smuzhiyun #define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ 202*4882a593Smuzhiyun #define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ 203*4882a593Smuzhiyun #define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* Bit definitions and macros for CIR */ 206*4882a593Smuzhiyun #define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ 207*4882a593Smuzhiyun #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ 208*4882a593Smuzhiyun #define CCM_CIR_PIN_MASK (0xFFC0) 209*4882a593Smuzhiyun #define CCM_CIR_PRN_MASK (0x003F) 210*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54450 (0x4F<<6) 211*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54451 (0x4D<<6) 212*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54452 (0x4B<<6) 213*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54453 (0x49<<6) 214*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54454 (0x4A<<6) 215*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54455 (0x48<<6) 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* Bit definitions and macros for MISCCR */ 218*4882a593Smuzhiyun #define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ 219*4882a593Smuzhiyun #define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */ 220*4882a593Smuzhiyun #define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */ 221*4882a593Smuzhiyun #define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ 222*4882a593Smuzhiyun #define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ 223*4882a593Smuzhiyun #define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ 224*4882a593Smuzhiyun #define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ 225*4882a593Smuzhiyun #define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */ 226*4882a593Smuzhiyun #define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */ 227*4882a593Smuzhiyun #define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ 228*4882a593Smuzhiyun #define CCM_MISCCR_BMT_65536 (0) 229*4882a593Smuzhiyun #define CCM_MISCCR_BMT_32768 (1) 230*4882a593Smuzhiyun #define CCM_MISCCR_BMT_16384 (2) 231*4882a593Smuzhiyun #define CCM_MISCCR_BMT_8192 (3) 232*4882a593Smuzhiyun #define CCM_MISCCR_BMT_4096 (4) 233*4882a593Smuzhiyun #define CCM_MISCCR_BMT_2048 (5) 234*4882a593Smuzhiyun #define CCM_MISCCR_BMT_1024 (6) 235*4882a593Smuzhiyun #define CCM_MISCCR_BMT_512 (7) 236*4882a593Smuzhiyun #define CCM_MISCCR_SSIPUS_UP (1) 237*4882a593Smuzhiyun #define CCM_MISCCR_SSIPUS_DOWN (0) 238*4882a593Smuzhiyun #define CCM_MISCCR_TIMDMA_TIM (1) 239*4882a593Smuzhiyun #define CCM_MISCCR_TIMDMA_SSI (0) 240*4882a593Smuzhiyun #define CCM_MISCCR_SSISRC_CLKIN (0) 241*4882a593Smuzhiyun #define CCM_MISCCR_SSISRC_PLL (1) 242*4882a593Smuzhiyun #define CCM_MISCCR_USBOC_ACTHI (0) 243*4882a593Smuzhiyun #define CCM_MISCCR_USBOV_ACTLO (1) 244*4882a593Smuzhiyun #define CCM_MISCCR_USBSRC_CLKIN (0) 245*4882a593Smuzhiyun #define CCM_MISCCR_USBSRC_PLL (1) 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /* Bit definitions and macros for CDR */ 248*4882a593Smuzhiyun #define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */ 249*4882a593Smuzhiyun #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */ 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun /* Bit definitions and macros for UOCSR */ 252*4882a593Smuzhiyun #define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */ 253*4882a593Smuzhiyun #define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */ 254*4882a593Smuzhiyun #define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ 255*4882a593Smuzhiyun #define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */ 256*4882a593Smuzhiyun #define CCM_UOCSR_SEND (0x0010) /* Session end */ 257*4882a593Smuzhiyun #define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ 258*4882a593Smuzhiyun #define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ 259*4882a593Smuzhiyun #define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ 260*4882a593Smuzhiyun #define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */ 261*4882a593Smuzhiyun #define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */ 262*4882a593Smuzhiyun #define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */ 263*4882a593Smuzhiyun #define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */ 264*4882a593Smuzhiyun #define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */ 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /********************************************************************* 267*4882a593Smuzhiyun * General Purpose I/O Module (GPIO) 268*4882a593Smuzhiyun *********************************************************************/ 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun /* Bit definitions and macros for PAR_FEC */ 271*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) 272*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) 273*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC1_UNMASK (0x8F) 274*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC1_MII (0x70) 275*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) 276*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) 277*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC1_ATA (0x10) 278*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC1_GPIO (0x00) 279*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC0_UNMASK (0xF8) 280*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC0_MII (0x07) 281*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) 282*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) 283*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC0_ULPI (0x01) 284*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC0_GPIO (0x00) 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun /* Bit definitions and macros for PAR_DMA */ 287*4882a593Smuzhiyun #define GPIO_PAR_DMA_DREQ0 (0x01) 288*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) 289*4882a593Smuzhiyun #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) 290*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) 291*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK1_UNMASK (0x3F) 292*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) 293*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) 294*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK1_GPIO (0x00) 295*4882a593Smuzhiyun #define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF) 296*4882a593Smuzhiyun #define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) 297*4882a593Smuzhiyun #define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) 298*4882a593Smuzhiyun #define GPIO_PAR_DMA_DREQ1_GPIO (0x00) 299*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK0_UNMASK (0xF3) 300*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) 301*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK0_PCS3 (0x08) 302*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) 303*4882a593Smuzhiyun #define GPIO_PAR_DMA_DACK0_GPIO (0x00) 304*4882a593Smuzhiyun #define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) 305*4882a593Smuzhiyun #define GPIO_PAR_DMA_DREQ0_GPIO (0x00) 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* Bit definitions and macros for PAR_FBCTL */ 308*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) 309*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_RW (0x20) 310*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TA (0x40) 311*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_OE (0x80) 312*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_OE_OE (0x80) 313*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_OE_GPIO (0x00) 314*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TA_TA (0x40) 315*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TA_GPIO (0x00) 316*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_RW_RW (0x20) 317*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_RW_GPIO (0x00) 318*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) 319*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TS_TS (0x18) 320*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TS_ALE (0x10) 321*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TS_TBST (0x08) 322*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TS_GPIO (0x80) 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun /* Bit definitions and macros for PAR_DSPI */ 325*4882a593Smuzhiyun #define GPIO_PAR_DSPI_SCK (0x01) 326*4882a593Smuzhiyun #define GPIO_PAR_DSPI_SOUT (0x02) 327*4882a593Smuzhiyun #define GPIO_PAR_DSPI_SIN (0x04) 328*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS0 (0x08) 329*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS1 (0x10) 330*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS2 (0x20) 331*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS5 (0x40) 332*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS5_PCS5 (0x40) 333*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS5_GPIO (0x00) 334*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS2_PCS2 (0x20) 335*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS2_GPIO (0x00) 336*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS1_PCS1 (0x10) 337*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS1_GPIO (0x00) 338*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS0_PCS0 (0x08) 339*4882a593Smuzhiyun #define GPIO_PAR_DSPI_PCS0_GPIO (0x00) 340*4882a593Smuzhiyun #define GPIO_PAR_DSPI_SIN_SIN (0x04) 341*4882a593Smuzhiyun #define GPIO_PAR_DSPI_SIN_GPIO (0x00) 342*4882a593Smuzhiyun #define GPIO_PAR_DSPI_SOUT_SOUT (0x02) 343*4882a593Smuzhiyun #define GPIO_PAR_DSPI_SOUT_GPIO (0x00) 344*4882a593Smuzhiyun #define GPIO_PAR_DSPI_SCK_SCK (0x01) 345*4882a593Smuzhiyun #define GPIO_PAR_DSPI_SCK_GPIO (0x00) 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun /* Bit definitions and macros for PAR_BE */ 348*4882a593Smuzhiyun #define GPIO_PAR_BE_BS0 (0x01) 349*4882a593Smuzhiyun #define GPIO_PAR_BE_BS1 (0x04) 350*4882a593Smuzhiyun #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) 351*4882a593Smuzhiyun #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) 352*4882a593Smuzhiyun #define GPIO_PAR_BE_BE3_UNMASK (0x3F) 353*4882a593Smuzhiyun #define GPIO_PAR_BE_BE3_BE3 (0xC0) 354*4882a593Smuzhiyun #define GPIO_PAR_BE_BE3_TSIZ1 (0x80) 355*4882a593Smuzhiyun #define GPIO_PAR_BE_BE3_GPIO (0x00) 356*4882a593Smuzhiyun #define GPIO_PAR_BE_BE2_UNMASK (0xCF) 357*4882a593Smuzhiyun #define GPIO_PAR_BE_BE2_BE2 (0x30) 358*4882a593Smuzhiyun #define GPIO_PAR_BE_BE2_TSIZ0 (0x20) 359*4882a593Smuzhiyun #define GPIO_PAR_BE_BE2_GPIO (0x00) 360*4882a593Smuzhiyun #define GPIO_PAR_BE_BE1_BE1 (0x04) 361*4882a593Smuzhiyun #define GPIO_PAR_BE_BE1_GPIO (0x00) 362*4882a593Smuzhiyun #define GPIO_PAR_BE_BE0_BE0 (0x01) 363*4882a593Smuzhiyun #define GPIO_PAR_BE_BE0_GPIO (0x00) 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun /* Bit definitions and macros for PAR_CS */ 366*4882a593Smuzhiyun #define GPIO_PAR_CS_CS1 (0x02) 367*4882a593Smuzhiyun #define GPIO_PAR_CS_CS2 (0x04) 368*4882a593Smuzhiyun #define GPIO_PAR_CS_CS3 (0x08) 369*4882a593Smuzhiyun #define GPIO_PAR_CS_CS3_CS3 (0x08) 370*4882a593Smuzhiyun #define GPIO_PAR_CS_CS3_GPIO (0x00) 371*4882a593Smuzhiyun #define GPIO_PAR_CS_CS2_CS2 (0x04) 372*4882a593Smuzhiyun #define GPIO_PAR_CS_CS2_GPIO (0x00) 373*4882a593Smuzhiyun #define GPIO_PAR_CS_CS1_CS1 (0x02) 374*4882a593Smuzhiyun #define GPIO_PAR_CS_CS1_GPIO (0x00) 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun /* Bit definitions and macros for PAR_TIMER */ 377*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) 378*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) 379*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) 380*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) 381*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) 382*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) 383*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) 384*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) 385*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) 386*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) 387*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) 388*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) 389*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) 390*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) 391*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) 392*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) 393*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) 394*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) 395*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) 396*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) 397*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) 398*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) 399*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) 400*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_GPIO (0x00) 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun /* Bit definitions and macros for PAR_USB */ 403*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) 404*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) 405*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3) 406*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) 407*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) 408*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) 409*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSEN_GPIO (0x00) 410*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC) 411*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) 412*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) 413*4882a593Smuzhiyun #define GPIO_PAR_USB_VBUSOC_GPIO (0x00) 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun /* Bit definitions and macros for PAR_UART */ 416*4882a593Smuzhiyun #define GPIO_PAR_UART_U0TXD (0x01) 417*4882a593Smuzhiyun #define GPIO_PAR_UART_U0RXD (0x02) 418*4882a593Smuzhiyun #define GPIO_PAR_UART_U0RTS (0x04) 419*4882a593Smuzhiyun #define GPIO_PAR_UART_U0CTS (0x08) 420*4882a593Smuzhiyun #define GPIO_PAR_UART_U1TXD (0x10) 421*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RXD (0x20) 422*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RTS (0x40) 423*4882a593Smuzhiyun #define GPIO_PAR_UART_U1CTS (0x80) 424*4882a593Smuzhiyun #define GPIO_PAR_UART_U1CTS_U1CTS (0x80) 425*4882a593Smuzhiyun #define GPIO_PAR_UART_U1CTS_GPIO (0x00) 426*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RTS_U1RTS (0x40) 427*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RTS_GPIO (0x00) 428*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RXD_U1RXD (0x20) 429*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RXD_GPIO (0x00) 430*4882a593Smuzhiyun #define GPIO_PAR_UART_U1TXD_U1TXD (0x10) 431*4882a593Smuzhiyun #define GPIO_PAR_UART_U1TXD_GPIO (0x00) 432*4882a593Smuzhiyun #define GPIO_PAR_UART_U0CTS_U0CTS (0x08) 433*4882a593Smuzhiyun #define GPIO_PAR_UART_U0CTS_GPIO (0x00) 434*4882a593Smuzhiyun #define GPIO_PAR_UART_U0RTS_U0RTS (0x04) 435*4882a593Smuzhiyun #define GPIO_PAR_UART_U0RTS_GPIO (0x00) 436*4882a593Smuzhiyun #define GPIO_PAR_UART_U0RXD_U0RXD (0x02) 437*4882a593Smuzhiyun #define GPIO_PAR_UART_U0RXD_GPIO (0x00) 438*4882a593Smuzhiyun #define GPIO_PAR_UART_U0TXD_U0TXD (0x01) 439*4882a593Smuzhiyun #define GPIO_PAR_UART_U0TXD_GPIO (0x00) 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun /* Bit definitions and macros for PAR_FECI2C */ 442*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) 443*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) 444*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO0 (0x0010) 445*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC0 (0x0040) 446*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) 447*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) 448*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF) 449*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) 450*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) 451*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) 452*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF) 453*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) 454*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) 455*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) 456*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) 457*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) 458*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) 459*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) 460*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3) 461*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_SCL (0x000C) 462*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) 463*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) 464*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC) 465*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_SDA (0x0003) 466*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) 467*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun /* Bit definitions and macros for PAR_SSI */ 470*4882a593Smuzhiyun #define GPIO_PAR_SSI_MCLK (0x0001) 471*4882a593Smuzhiyun #define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) 472*4882a593Smuzhiyun #define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) 473*4882a593Smuzhiyun #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) 474*4882a593Smuzhiyun #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) 475*4882a593Smuzhiyun #define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF) 476*4882a593Smuzhiyun #define GPIO_PAR_SSI_BCLK_BCLK (0x0300) 477*4882a593Smuzhiyun #define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) 478*4882a593Smuzhiyun #define GPIO_PAR_SSI_BCLK_GPIO (0x0000) 479*4882a593Smuzhiyun #define GPIO_PAR_SSI_FS_UNMASK (0xFF3F) 480*4882a593Smuzhiyun #define GPIO_PAR_SSI_FS_FS (0x00C0) 481*4882a593Smuzhiyun #define GPIO_PAR_SSI_FS_U1RTS (0x0080) 482*4882a593Smuzhiyun #define GPIO_PAR_SSI_FS_GPIO (0x0000) 483*4882a593Smuzhiyun #define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF) 484*4882a593Smuzhiyun #define GPIO_PAR_SSI_SRXD_SRXD (0x0030) 485*4882a593Smuzhiyun #define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) 486*4882a593Smuzhiyun #define GPIO_PAR_SSI_SRXD_GPIO (0x0000) 487*4882a593Smuzhiyun #define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3) 488*4882a593Smuzhiyun #define GPIO_PAR_SSI_STXD_STXD (0x000C) 489*4882a593Smuzhiyun #define GPIO_PAR_SSI_STXD_U1TXD (0x0008) 490*4882a593Smuzhiyun #define GPIO_PAR_SSI_STXD_GPIO (0x0000) 491*4882a593Smuzhiyun #define GPIO_PAR_SSI_MCLK_MCLK (0x0001) 492*4882a593Smuzhiyun #define GPIO_PAR_SSI_MCLK_GPIO (0x0000) 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun /* Bit definitions and macros for PAR_ATA */ 495*4882a593Smuzhiyun #define GPIO_PAR_ATA_IORDY (0x0001) 496*4882a593Smuzhiyun #define GPIO_PAR_ATA_DMARQ (0x0002) 497*4882a593Smuzhiyun #define GPIO_PAR_ATA_RESET (0x0004) 498*4882a593Smuzhiyun #define GPIO_PAR_ATA_DA0 (0x0020) 499*4882a593Smuzhiyun #define GPIO_PAR_ATA_DA1 (0x0040) 500*4882a593Smuzhiyun #define GPIO_PAR_ATA_DA2 (0x0080) 501*4882a593Smuzhiyun #define GPIO_PAR_ATA_CS0 (0x0100) 502*4882a593Smuzhiyun #define GPIO_PAR_ATA_CS1 (0x0200) 503*4882a593Smuzhiyun #define GPIO_PAR_ATA_BUFEN (0x0400) 504*4882a593Smuzhiyun #define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) 505*4882a593Smuzhiyun #define GPIO_PAR_ATA_BUFEN_GPIO (0x0000) 506*4882a593Smuzhiyun #define GPIO_PAR_ATA_CS1_CS1 (0x0200) 507*4882a593Smuzhiyun #define GPIO_PAR_ATA_CS1_GPIO (0x0000) 508*4882a593Smuzhiyun #define GPIO_PAR_ATA_CS0_CS0 (0x0100) 509*4882a593Smuzhiyun #define GPIO_PAR_ATA_CS0_GPIO (0x0000) 510*4882a593Smuzhiyun #define GPIO_PAR_ATA_DA2_DA2 (0x0080) 511*4882a593Smuzhiyun #define GPIO_PAR_ATA_DA2_GPIO (0x0000) 512*4882a593Smuzhiyun #define GPIO_PAR_ATA_DA1_DA1 (0x0040) 513*4882a593Smuzhiyun #define GPIO_PAR_ATA_DA1_GPIO (0x0000) 514*4882a593Smuzhiyun #define GPIO_PAR_ATA_DA0_DA0 (0x0020) 515*4882a593Smuzhiyun #define GPIO_PAR_ATA_DA0_GPIO (0x0000) 516*4882a593Smuzhiyun #define GPIO_PAR_ATA_RESET_RESET (0x0004) 517*4882a593Smuzhiyun #define GPIO_PAR_ATA_RESET_GPIO (0x0000) 518*4882a593Smuzhiyun #define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) 519*4882a593Smuzhiyun #define GPIO_PAR_ATA_DMARQ_GPIO (0x0000) 520*4882a593Smuzhiyun #define GPIO_PAR_ATA_IORDY_IORDY (0x0001) 521*4882a593Smuzhiyun #define GPIO_PAR_ATA_IORDY_GPIO (0x0000) 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun /* Bit definitions and macros for PAR_IRQ */ 524*4882a593Smuzhiyun #define GPIO_PAR_IRQ_IRQ1 (0x02) 525*4882a593Smuzhiyun #define GPIO_PAR_IRQ_IRQ4 (0x10) 526*4882a593Smuzhiyun #define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) 527*4882a593Smuzhiyun #define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) 528*4882a593Smuzhiyun #define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) 529*4882a593Smuzhiyun #define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun /* Bit definitions and macros for PAR_PCI */ 532*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ0 (0x0001) 533*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ1 (0x0004) 534*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ2 (0x0010) 535*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) 536*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT0 (0x0100) 537*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT1 (0x0400) 538*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT2 (0x1000) 539*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) 540*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF) 541*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) 542*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) 543*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT3_GPIO (0x0000) 544*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT2_GNT2 (0x1000) 545*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT2_GPIO (0x0000) 546*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT1_GNT1 (0x0400) 547*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT1_GPIO (0x0000) 548*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) 549*4882a593Smuzhiyun #define GPIO_PAR_PCI_GNT0_GPIO (0x0000) 550*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F) 551*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) 552*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) 553*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ3_GPIO (0x0000) 554*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ2_REQ2 (0x0010) 555*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ2_GPIO (0x0000) 556*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ1_REQ1 (0x0040) 557*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ1_GPIO (0x0000) 558*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ0_REQ0 (0x0001) 559*4882a593Smuzhiyun #define GPIO_PAR_PCI_REQ0_GPIO (0x0000) 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun /* Bit definitions and macros for MSCR_SDRAM */ 562*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) 563*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) 564*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) 565*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) 566*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F) 567*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) 568*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) 569*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) 570*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) 571*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF) 572*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) 573*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) 574*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) 575*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) 576*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) 577*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) 578*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) 579*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) 580*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) 581*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) 582*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) 583*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) 584*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) 585*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun /* Bit definitions and macros for MSCR_PCI */ 588*4882a593Smuzhiyun #define GPIO_MSCR_PCI_PCI (0x01) 589*4882a593Smuzhiyun #define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) 590*4882a593Smuzhiyun #define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_I2C */ 593*4882a593Smuzhiyun #define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) 594*4882a593Smuzhiyun #define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) 595*4882a593Smuzhiyun #define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) 596*4882a593Smuzhiyun #define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) 597*4882a593Smuzhiyun #define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) 598*4882a593Smuzhiyun 599*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_FLEXBUS */ 600*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) 601*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) 602*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) 603*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) 604*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) 605*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80) 606*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) 607*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) 608*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) 609*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) 610*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) 611*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) 612*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) 613*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) 614*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) 615*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) 616*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) 617*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) 618*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) 619*4882a593Smuzhiyun #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_FEC */ 622*4882a593Smuzhiyun #define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) 623*4882a593Smuzhiyun #define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) 624*4882a593Smuzhiyun #define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) 625*4882a593Smuzhiyun #define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) 626*4882a593Smuzhiyun #define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) 627*4882a593Smuzhiyun #define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) 628*4882a593Smuzhiyun #define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) 629*4882a593Smuzhiyun #define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) 630*4882a593Smuzhiyun #define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) 631*4882a593Smuzhiyun #define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) 632*4882a593Smuzhiyun 633*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_UART */ 634*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART0(x) (((x)&0x03)) 635*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) 636*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) 637*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) 638*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) 639*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) 640*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) 641*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) 642*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) 643*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_DSPI */ 646*4882a593Smuzhiyun #define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) 647*4882a593Smuzhiyun #define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) 648*4882a593Smuzhiyun #define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) 649*4882a593Smuzhiyun #define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) 650*4882a593Smuzhiyun #define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) 651*4882a593Smuzhiyun 652*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_TIMER */ 653*4882a593Smuzhiyun #define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) 654*4882a593Smuzhiyun #define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) 655*4882a593Smuzhiyun #define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) 656*4882a593Smuzhiyun #define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) 657*4882a593Smuzhiyun #define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_SSI */ 660*4882a593Smuzhiyun #define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) 661*4882a593Smuzhiyun #define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) 662*4882a593Smuzhiyun #define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) 663*4882a593Smuzhiyun #define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) 664*4882a593Smuzhiyun #define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_DMA */ 667*4882a593Smuzhiyun #define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) 668*4882a593Smuzhiyun #define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) 669*4882a593Smuzhiyun #define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) 670*4882a593Smuzhiyun #define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) 671*4882a593Smuzhiyun #define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_DEBUG */ 674*4882a593Smuzhiyun #define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) 675*4882a593Smuzhiyun #define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) 676*4882a593Smuzhiyun #define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) 677*4882a593Smuzhiyun #define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) 678*4882a593Smuzhiyun #define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) 679*4882a593Smuzhiyun 680*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_RESET */ 681*4882a593Smuzhiyun #define GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) 682*4882a593Smuzhiyun #define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) 683*4882a593Smuzhiyun #define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) 684*4882a593Smuzhiyun #define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) 685*4882a593Smuzhiyun #define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) 686*4882a593Smuzhiyun 687*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_IRQ */ 688*4882a593Smuzhiyun #define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) 689*4882a593Smuzhiyun #define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) 690*4882a593Smuzhiyun #define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) 691*4882a593Smuzhiyun #define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) 692*4882a593Smuzhiyun #define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_USB */ 695*4882a593Smuzhiyun #define GPIO_DSCR_USB_USB(x) (((x)&0x03)) 696*4882a593Smuzhiyun #define GPIO_DSCR_USB_USB_LOAD_50PF (0x03) 697*4882a593Smuzhiyun #define GPIO_DSCR_USB_USB_LOAD_30PF (0x02) 698*4882a593Smuzhiyun #define GPIO_DSCR_USB_USB_LOAD_20PF (0x01) 699*4882a593Smuzhiyun #define GPIO_DSCR_USB_USB_LOAD_10PF (0x00) 700*4882a593Smuzhiyun 701*4882a593Smuzhiyun /* Bit definitions and macros for DSCR_ATA */ 702*4882a593Smuzhiyun #define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) 703*4882a593Smuzhiyun #define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) 704*4882a593Smuzhiyun #define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) 705*4882a593Smuzhiyun #define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) 706*4882a593Smuzhiyun #define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun /********************************************************************* 709*4882a593Smuzhiyun * SDRAM Controller (SDRAMC) 710*4882a593Smuzhiyun *********************************************************************/ 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun /* Bit definitions and macros for SDMR */ 713*4882a593Smuzhiyun #define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ 714*4882a593Smuzhiyun #define SDRAMC_SDMR_CMD (0x00010000) /* Command */ 715*4882a593Smuzhiyun #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ 716*4882a593Smuzhiyun #define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ 717*4882a593Smuzhiyun #define SDRAMC_SDMR_BK_LMR (0x00000000) 718*4882a593Smuzhiyun #define SDRAMC_SDMR_BK_LEMR (0x40000000) 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun /* Bit definitions and macros for SDCR */ 721*4882a593Smuzhiyun #define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ 722*4882a593Smuzhiyun #define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ 723*4882a593Smuzhiyun #define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ 724*4882a593Smuzhiyun #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ 725*4882a593Smuzhiyun #define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ 726*4882a593Smuzhiyun #define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ 727*4882a593Smuzhiyun #define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ 728*4882a593Smuzhiyun #define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ 729*4882a593Smuzhiyun #define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ 730*4882a593Smuzhiyun #define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ 731*4882a593Smuzhiyun #define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ 732*4882a593Smuzhiyun #define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ 733*4882a593Smuzhiyun #define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ 734*4882a593Smuzhiyun #define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun /* Bit definitions and macros for SDCFG1 */ 737*4882a593Smuzhiyun #define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ 738*4882a593Smuzhiyun #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ 739*4882a593Smuzhiyun #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ 740*4882a593Smuzhiyun #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ 741*4882a593Smuzhiyun #define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ 742*4882a593Smuzhiyun #define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ 743*4882a593Smuzhiyun #define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun /* Bit definitions and macros for SDCFG2 */ 746*4882a593Smuzhiyun #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ 747*4882a593Smuzhiyun #define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ 748*4882a593Smuzhiyun #define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ 749*4882a593Smuzhiyun #define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun /* Bit definitions and macros for SDCS group */ 752*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ 753*4882a593Smuzhiyun #define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ 754*4882a593Smuzhiyun #define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) 755*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) 756*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) 757*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) 758*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) 759*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) 760*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) 761*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) 762*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) 763*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) 764*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) 765*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) 766*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) 767*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) 768*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) 769*4882a593Smuzhiyun 770*4882a593Smuzhiyun /********************************************************************* 771*4882a593Smuzhiyun * Phase Locked Loop (PLL) 772*4882a593Smuzhiyun *********************************************************************/ 773*4882a593Smuzhiyun 774*4882a593Smuzhiyun /* Bit definitions and macros for PCR */ 775*4882a593Smuzhiyun #define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ 776*4882a593Smuzhiyun #define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */ 777*4882a593Smuzhiyun #define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */ 778*4882a593Smuzhiyun #define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */ 779*4882a593Smuzhiyun #define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ 780*4882a593Smuzhiyun #define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ 781*4882a593Smuzhiyun #define PLL_PCR_PFDR_MASK (0x000F0000) 782*4882a593Smuzhiyun #define PLL_PCR_OUTDIV5_MASK (0x000F0000) 783*4882a593Smuzhiyun #define PLL_PCR_OUTDIV4_MASK (0x0000F000) 784*4882a593Smuzhiyun #define PLL_PCR_OUTDIV3_MASK (0x00000F00) 785*4882a593Smuzhiyun #define PLL_PCR_OUTDIV2_MASK (0x000000F0) 786*4882a593Smuzhiyun #define PLL_PCR_OUTDIV1_MASK (0x0000000F) 787*4882a593Smuzhiyun 788*4882a593Smuzhiyun /* Bit definitions and macros for PSR */ 789*4882a593Smuzhiyun #define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ 790*4882a593Smuzhiyun #define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ 791*4882a593Smuzhiyun #define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ 792*4882a593Smuzhiyun #define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ 793*4882a593Smuzhiyun 794*4882a593Smuzhiyun /********************************************************************* 795*4882a593Smuzhiyun * PCI 796*4882a593Smuzhiyun *********************************************************************/ 797*4882a593Smuzhiyun 798*4882a593Smuzhiyun /* Bit definitions and macros for SCR */ 799*4882a593Smuzhiyun #define PCI_SCR_PE (0x80000000) /* Parity Error detected */ 800*4882a593Smuzhiyun #define PCI_SCR_SE (0x40000000) /* System error signalled */ 801*4882a593Smuzhiyun #define PCI_SCR_MA (0x20000000) /* Master aboart received */ 802*4882a593Smuzhiyun #define PCI_SCR_TR (0x10000000) /* Target abort received */ 803*4882a593Smuzhiyun #define PCI_SCR_TS (0x08000000) /* Target abort signalled */ 804*4882a593Smuzhiyun #define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ 805*4882a593Smuzhiyun #define PCI_SCR_DP (0x01000000) /* Master data parity err */ 806*4882a593Smuzhiyun #define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ 807*4882a593Smuzhiyun #define PCI_SCR_R (0x00400000) /* Reserved */ 808*4882a593Smuzhiyun #define PCI_SCR_66M (0x00200000) /* 66Mhz */ 809*4882a593Smuzhiyun #define PCI_SCR_C (0x00100000) /* Capabilities list */ 810*4882a593Smuzhiyun #define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ 811*4882a593Smuzhiyun #define PCI_SCR_S (0x00000100) /* SERR enable */ 812*4882a593Smuzhiyun #define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ 813*4882a593Smuzhiyun #define PCI_SCR_PER (0x00000040) /* Parity error response */ 814*4882a593Smuzhiyun #define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ 815*4882a593Smuzhiyun #define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ 816*4882a593Smuzhiyun #define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ 817*4882a593Smuzhiyun #define PCI_SCR_B (0x00000004) /* Bus master enable */ 818*4882a593Smuzhiyun #define PCI_SCR_M (0x00000002) /* Memory access control */ 819*4882a593Smuzhiyun #define PCI_SCR_IO (0x00000001) /* I/O access control */ 820*4882a593Smuzhiyun 821*4882a593Smuzhiyun #define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ 822*4882a593Smuzhiyun #define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ 823*4882a593Smuzhiyun #define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ 824*4882a593Smuzhiyun #define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ 825*4882a593Smuzhiyun 826*4882a593Smuzhiyun #define PCI_BAR_BAR0(x) (x & 0xFFFC0000) 827*4882a593Smuzhiyun #define PCI_BAR_BAR1(x) (x & 0xFFF00000) 828*4882a593Smuzhiyun #define PCI_BAR_BAR2(x) (x & 0xFFC00000) 829*4882a593Smuzhiyun #define PCI_BAR_BAR3(x) (x & 0xFF000000) 830*4882a593Smuzhiyun #define PCI_BAR_BAR4(x) (x & 0xF8000000) 831*4882a593Smuzhiyun #define PCI_BAR_BAR5(x) (x & 0xE0000000) 832*4882a593Smuzhiyun #define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ 833*4882a593Smuzhiyun #define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ 834*4882a593Smuzhiyun #define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ 835*4882a593Smuzhiyun 836*4882a593Smuzhiyun #define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ 837*4882a593Smuzhiyun #define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ 838*4882a593Smuzhiyun #define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ 839*4882a593Smuzhiyun #define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ 840*4882a593Smuzhiyun 841*4882a593Smuzhiyun #define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ 842*4882a593Smuzhiyun #define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ 843*4882a593Smuzhiyun #define PCI_GSCR_SE (0x10000000) /* SERR detected */ 844*4882a593Smuzhiyun #define PCI_GSCR_ER (0x08000000) /* Error response detected */ 845*4882a593Smuzhiyun #define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ 846*4882a593Smuzhiyun #define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ 847*4882a593Smuzhiyun #define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ 848*4882a593Smuzhiyun #define PCI_GSCR_PR (0x00000001) /* PCI reset */ 849*4882a593Smuzhiyun 850*4882a593Smuzhiyun #define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ 851*4882a593Smuzhiyun #define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ 852*4882a593Smuzhiyun #define PCI_TCR1_P (0x00010000) /* Prefetch reads */ 853*4882a593Smuzhiyun #define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ 854*4882a593Smuzhiyun 855*4882a593Smuzhiyun #define PCI_TCR2_B5E (0x00002000) /* */ 856*4882a593Smuzhiyun #define PCI_TCR2_B4E (0x00001000) /* */ 857*4882a593Smuzhiyun #define PCI_TCR2_B3E (0x00000800) /* */ 858*4882a593Smuzhiyun #define PCI_TCR2_B2E (0x00000400) /* */ 859*4882a593Smuzhiyun #define PCI_TCR2_B1E (0x00000200) /* */ 860*4882a593Smuzhiyun #define PCI_TCR2_B0E (0x00000100) /* */ 861*4882a593Smuzhiyun #define PCI_TCR2_CR (0x00000001) /* */ 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun #define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) 864*4882a593Smuzhiyun #define PCI_TBATR_EN (0x00000001) /* Enable */ 865*4882a593Smuzhiyun 866*4882a593Smuzhiyun #define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ 867*4882a593Smuzhiyun #define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ 868*4882a593Smuzhiyun #define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ 869*4882a593Smuzhiyun #define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ 870*4882a593Smuzhiyun #define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ 871*4882a593Smuzhiyun #define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ 872*4882a593Smuzhiyun #define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ 873*4882a593Smuzhiyun #define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ 874*4882a593Smuzhiyun #define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ 875*4882a593Smuzhiyun #define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ 876*4882a593Smuzhiyun #define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ 877*4882a593Smuzhiyun #define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ 878*4882a593Smuzhiyun #define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ 879*4882a593Smuzhiyun #define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ 880*4882a593Smuzhiyun #define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ 881*4882a593Smuzhiyun 882*4882a593Smuzhiyun #define PCI_ICR_REE (0x04000000) /* Retry error enable */ 883*4882a593Smuzhiyun #define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ 884*4882a593Smuzhiyun #define PCI_ICR_TAE (0x01000000) /* Target abort enable */ 885*4882a593Smuzhiyun #define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF) 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun /********************************************************************/ 888*4882a593Smuzhiyun 889*4882a593Smuzhiyun #endif /* __MCF5445X__ */ 890