1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * MCF5441X Internal Memory Map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2010-2012 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MCF5441X__ 11*4882a593Smuzhiyun #define __MCF5441X__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Interrupt Controller (INTC) */ 14*4882a593Smuzhiyun #define INT0_LO_RSVD0 (0) 15*4882a593Smuzhiyun #define INT0_LO_EPORT1 (1) 16*4882a593Smuzhiyun #define INT0_LO_EPORT2 (2) 17*4882a593Smuzhiyun #define INT0_LO_EPORT3 (3) 18*4882a593Smuzhiyun #define INT0_LO_EPORT4 (4) 19*4882a593Smuzhiyun #define INT0_LO_EPORT5 (5) 20*4882a593Smuzhiyun #define INT0_LO_EPORT6 (6) 21*4882a593Smuzhiyun #define INT0_LO_EPORT7 (7) 22*4882a593Smuzhiyun #define INT0_LO_EDMA_00 (8) 23*4882a593Smuzhiyun #define INT0_LO_EDMA_01 (9) 24*4882a593Smuzhiyun #define INT0_LO_EDMA_02 (10) 25*4882a593Smuzhiyun #define INT0_LO_EDMA_03 (11) 26*4882a593Smuzhiyun #define INT0_LO_EDMA_04 (12) 27*4882a593Smuzhiyun #define INT0_LO_EDMA_05 (13) 28*4882a593Smuzhiyun #define INT0_LO_EDMA_06 (14) 29*4882a593Smuzhiyun #define INT0_LO_EDMA_07 (15) 30*4882a593Smuzhiyun #define INT0_LO_EDMA_08 (16) 31*4882a593Smuzhiyun #define INT0_LO_EDMA_09 (17) 32*4882a593Smuzhiyun #define INT0_LO_EDMA_10 (18) 33*4882a593Smuzhiyun #define INT0_LO_EDMA_11 (19) 34*4882a593Smuzhiyun #define INT0_LO_EDMA_12 (20) 35*4882a593Smuzhiyun #define INT0_LO_EDMA_13 (21) 36*4882a593Smuzhiyun #define INT0_LO_EDMA_14 (22) 37*4882a593Smuzhiyun #define INT0_LO_EDMA_15 (23) 38*4882a593Smuzhiyun #define INT0_LO_EDMA_ERR (24) 39*4882a593Smuzhiyun #define INT0_LO_SCM (25) 40*4882a593Smuzhiyun #define INT0_LO_UART0 (26) 41*4882a593Smuzhiyun #define INT0_LO_UART1 (27) 42*4882a593Smuzhiyun #define INT0_LO_UART2 (28) 43*4882a593Smuzhiyun #define INT0_LO_UART3 (29) 44*4882a593Smuzhiyun #define INT0_LO_I2C0 (30) 45*4882a593Smuzhiyun #define INT0_LO_DSPI0 (31) 46*4882a593Smuzhiyun #define INT0_HI_DTMR0 (32) 47*4882a593Smuzhiyun #define INT0_HI_DTMR1 (33) 48*4882a593Smuzhiyun #define INT0_HI_DTMR2 (34) 49*4882a593Smuzhiyun #define INT0_HI_DTMR3 (35) 50*4882a593Smuzhiyun #define INT0_HI_MACNET0_TXF (36) 51*4882a593Smuzhiyun #define INT0_HI_MACNET0_TXB (37) 52*4882a593Smuzhiyun #define INT0_HI_MACNET0_UN (38) 53*4882a593Smuzhiyun #define INT0_HI_MACNET0_RL (39) 54*4882a593Smuzhiyun #define INT0_HI_MACNET0_RXF (40) 55*4882a593Smuzhiyun #define INT0_HI_MACNET0_RXB (41) 56*4882a593Smuzhiyun #define INT0_HI_MACNET0_MII (42) 57*4882a593Smuzhiyun #define INT0_HI_MACNET0_LC (43) 58*4882a593Smuzhiyun /* not used 44 */ 59*4882a593Smuzhiyun #define INT0_HI_MACNET0_GRA (45) 60*4882a593Smuzhiyun #define INT0_HI_MACNET0_EBERR (46) 61*4882a593Smuzhiyun #define INT0_HI_MACNET0_BABT (47) 62*4882a593Smuzhiyun #define INT0_HI_MACNET0_BABR (48) 63*4882a593Smuzhiyun #define INT0_HI_MACNET1_TXF (49) 64*4882a593Smuzhiyun #define INT0_HI_MACNET1_TXB (50) 65*4882a593Smuzhiyun #define INT0_HI_MACNET1_UN (51) 66*4882a593Smuzhiyun #define INT0_HI_MACNET1_RL (52) 67*4882a593Smuzhiyun #define INT0_HI_MACNET1_RXF (53) 68*4882a593Smuzhiyun #define INT0_HI_MACNET1_RXB (54) 69*4882a593Smuzhiyun #define INT0_HI_MACNET1_MII (55) 70*4882a593Smuzhiyun #define INT0_HI_MACNET1_LC (56) 71*4882a593Smuzhiyun /* not used 57 */ 72*4882a593Smuzhiyun #define INT0_HI_MACNET1_GRA (58) 73*4882a593Smuzhiyun #define INT0_HI_MACNET1_EBERR (59) 74*4882a593Smuzhiyun #define INT0_HI_MACNET1_BABT (60) 75*4882a593Smuzhiyun #define INT0_HI_MACNET1_BABR (61) 76*4882a593Smuzhiyun #define INT0_HI_SCMIR (62) 77*4882a593Smuzhiyun #define INT0_HI_OW (63) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define INT1_LO_CAN0_IFG (0) 80*4882a593Smuzhiyun #define INT1_LO_CAN0_BOFF (1) 81*4882a593Smuzhiyun /* not used 2 */ 82*4882a593Smuzhiyun #define INT1_LO_CAN0_TXRXWRN (3) 83*4882a593Smuzhiyun #define INT1_LO_CAN1_IFG (4) 84*4882a593Smuzhiyun #define INT1_LO_CAN1_BOFF (5) 85*4882a593Smuzhiyun /* not used 6 */ 86*4882a593Smuzhiyun #define INT1_LO_CAN1_TXRXWRN (7) 87*4882a593Smuzhiyun #define INT1_LO_EDMA_16 (8) 88*4882a593Smuzhiyun #define INT1_LO_EDMA_17 (9) 89*4882a593Smuzhiyun #define INT1_LO_EDMA_18 (10) 90*4882a593Smuzhiyun #define INT1_LO_EDMA_19 (11) 91*4882a593Smuzhiyun #define INT1_LO_EDMA_20 (12) 92*4882a593Smuzhiyun #define INT1_LO_EDMA_21 (13) 93*4882a593Smuzhiyun #define INT1_LO_EDMA_22 (14) 94*4882a593Smuzhiyun #define INT1_LO_EDMA_23 (15) 95*4882a593Smuzhiyun #define INT1_LO_EDMA_24 (16) 96*4882a593Smuzhiyun #define INT1_LO_EDMA_25 (17) 97*4882a593Smuzhiyun #define INT1_LO_EDMA_26 (18) 98*4882a593Smuzhiyun #define INT1_LO_EDMA_27 (19) 99*4882a593Smuzhiyun #define INT1_LO_EDMA_28 (20) 100*4882a593Smuzhiyun #define INT1_LO_EDMA_29 (21) 101*4882a593Smuzhiyun #define INT1_LO_EDMA_30 (22) 102*4882a593Smuzhiyun #define INT1_LO_EDMA_31 (23) 103*4882a593Smuzhiyun #define INT1_LO_EDMA_32 (24) 104*4882a593Smuzhiyun #define INT1_LO_EDMA_33 (25) 105*4882a593Smuzhiyun #define INT1_LO_EDMA_34 (26) 106*4882a593Smuzhiyun #define INT1_LO_EDMA_35 (27) 107*4882a593Smuzhiyun #define INT1_LO_EDMA_36 (28) 108*4882a593Smuzhiyun #define INT1_LO_EDMA_37 (29) 109*4882a593Smuzhiyun #define INT1_LO_EDMA_38 (30) 110*4882a593Smuzhiyun #define INT1_LO_EDMA_39 (31) 111*4882a593Smuzhiyun #define INT1_LO_EDMA_40 (32) 112*4882a593Smuzhiyun #define INT1_HI_EDMA_41 (33) 113*4882a593Smuzhiyun #define INT1_HI_EDMA_42 (34) 114*4882a593Smuzhiyun #define INT1_HI_EDMA_43 (35) 115*4882a593Smuzhiyun #define INT1_HI_EDMA_44 (36) 116*4882a593Smuzhiyun #define INT1_HI_EDMA_45 (37) 117*4882a593Smuzhiyun #define INT1_HI_EDMA_46 (38) 118*4882a593Smuzhiyun #define INT1_HI_EDMA_47 (39) 119*4882a593Smuzhiyun #define INT1_HI_EDMA_48 (40) 120*4882a593Smuzhiyun #define INT1_HI_EDMA_49 (41) 121*4882a593Smuzhiyun #define INT1_HI_EDMA_50 (42) 122*4882a593Smuzhiyun #define INT1_HI_EDMA_51 (43) 123*4882a593Smuzhiyun #define INT1_HI_EDMA_52 (44) 124*4882a593Smuzhiyun #define INT1_HI_EDMA_53 (45) 125*4882a593Smuzhiyun #define INT1_HI_EDMA_54 (46) 126*4882a593Smuzhiyun #define INT1_HI_EDMA_55 (47) 127*4882a593Smuzhiyun #define INT1_HI_UART4 (48) 128*4882a593Smuzhiyun #define INT1_HI_UART5 (49) 129*4882a593Smuzhiyun #define INT1_HI_UART6 (50) 130*4882a593Smuzhiyun #define INT1_HI_UART7 (51) 131*4882a593Smuzhiyun #define INT1_HI_UART8 (52) 132*4882a593Smuzhiyun #define INT1_HI_UART9 (53) 133*4882a593Smuzhiyun #define INT1_HI_DSPI1 (54) 134*4882a593Smuzhiyun #define INT1_HI_DSPI2 (55) 135*4882a593Smuzhiyun #define INT1_HI_DSPI3 (56) 136*4882a593Smuzhiyun #define INT1_HI_I2C1 (57) 137*4882a593Smuzhiyun #define INT1_HI_I2C2 (58) 138*4882a593Smuzhiyun #define INT1_HI_I2C3 (59) 139*4882a593Smuzhiyun #define INT1_HI_I2C4 (60) 140*4882a593Smuzhiyun #define INT1_HI_I2C5 (61) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define INT2_LO_EDMA56_63 (0) 143*4882a593Smuzhiyun #define INT2_LO_PWM_SM0SR_CF (1) 144*4882a593Smuzhiyun #define INT2_LO_PWM_SM1SR_CF (2) 145*4882a593Smuzhiyun #define INT2_LO_PWM_SM2SR_CF (3) 146*4882a593Smuzhiyun #define INT2_LO_PWM_SM3SR_CF (4) 147*4882a593Smuzhiyun #define INT2_LO_PWM_SM0SR_RF (5) 148*4882a593Smuzhiyun #define INT2_LO_PWM_SM1SR_RF (6) 149*4882a593Smuzhiyun #define INT2_LO_PWM_SM2SR_RF (7) 150*4882a593Smuzhiyun #define INT2_LO_PWM_SM3SR_RF (8) 151*4882a593Smuzhiyun #define INT2_LO_PWM_FSR (9) 152*4882a593Smuzhiyun #define INT2_LO_PWM_SMSR_REF (10) 153*4882a593Smuzhiyun #define INT2_LO_PLL_SR_LOCF (11) 154*4882a593Smuzhiyun #define INT2_LO_PLL_SR_LOLF (12) 155*4882a593Smuzhiyun #define INT2_LO_PIT0_PIF (13) 156*4882a593Smuzhiyun #define INT2_LO_PIT1_PIF (14) 157*4882a593Smuzhiyun #define INT2_LO_PIT2_PIF (15) 158*4882a593Smuzhiyun #define INT2_LO_PIT3_PIF (16) 159*4882a593Smuzhiyun #define INT2_LO_USBOTG_USBSTS (17) 160*4882a593Smuzhiyun #define INT2_LO_USBH_USBSTS (18) 161*4882a593Smuzhiyun /* not used 19-20 */ 162*4882a593Smuzhiyun #define INT2_LO_SSI0 (21) 163*4882a593Smuzhiyun #define INT2_LO_SSI1 (22) 164*4882a593Smuzhiyun #define INT2_LO_NFC (23) 165*4882a593Smuzhiyun /* not used 24-25 */ 166*4882a593Smuzhiyun #define INT2_LO_RTC (26) 167*4882a593Smuzhiyun #define INT2_LO_CCM_UOCSR (27) 168*4882a593Smuzhiyun #define INT2_LO_RNG_EI (28) 169*4882a593Smuzhiyun #define INT2_LO_SIM1_DATA (29) 170*4882a593Smuzhiyun #define INT2_LO_SIM1 (30) 171*4882a593Smuzhiyun #define INT2_LO_SDHC (31) 172*4882a593Smuzhiyun /* not used 32-37 */ 173*4882a593Smuzhiyun #define INT2_HI_L2SW_BERR (38) 174*4882a593Smuzhiyun #define INT2_HI_L2SW_RXB (39) 175*4882a593Smuzhiyun #define INT2_HI_L2SW_RXF (40) 176*4882a593Smuzhiyun #define INT2_HI_L2SW_TXB (41) 177*4882a593Smuzhiyun #define INT2_HI_L2SW_TXF (42) 178*4882a593Smuzhiyun #define INT2_HI_L2SW_QM (43) 179*4882a593Smuzhiyun #define INT2_HI_L2SW_OD0 (44) 180*4882a593Smuzhiyun #define INT2_HI_L2SW_OD1 (45) 181*4882a593Smuzhiyun #define INT2_HI_L2SW_OD2 (46) 182*4882a593Smuzhiyun #define INT2_HI_L2SW_LRN (47) 183*4882a593Smuzhiyun #define INT2_HI_MACNET0_TS (48) 184*4882a593Smuzhiyun #define INT2_HI_MACNET0_WAKE (49) 185*4882a593Smuzhiyun #define INT2_HI_MACNET0_PLR (50) 186*4882a593Smuzhiyun /* not used 51-54 */ 187*4882a593Smuzhiyun #define INT2_HI_MACNET1_TS (51) 188*4882a593Smuzhiyun #define INT2_HI_MACNET1_WAKE (52) 189*4882a593Smuzhiyun #define INT2_HI_MACNET1_PLR (53) 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* Serial Boot Facility (SBF) */ 192*4882a593Smuzhiyun #define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) 193*4882a593Smuzhiyun #define SBF_SBFCR_FR (0x0010) 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* Reset Controller Module (RCM) */ 196*4882a593Smuzhiyun #define RCM_RCR_SOFTRST (0x80) 197*4882a593Smuzhiyun #define RCM_RCR_FRCRSTOUT (0x40) 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define RCM_RSR_SOFT (0x20) 200*4882a593Smuzhiyun #define RCM_RSR_LOC (0x10) 201*4882a593Smuzhiyun #define RCM_RSR_POR (0x08) 202*4882a593Smuzhiyun #define RCM_RSR_EXT (0x04) 203*4882a593Smuzhiyun #define RCM_RSR_WDR_CORE (0x02) 204*4882a593Smuzhiyun #define RCM_RSR_LOL (0x01) 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* Chip Configuration Module (CCM) */ 207*4882a593Smuzhiyun #define CCM_CCR_BOOTMOD (0xC000) 208*4882a593Smuzhiyun #define CCM_CCR_PLLMULT (0x0FC0) 209*4882a593Smuzhiyun #define CCM_CCR_BOOTPS (0x0030) 210*4882a593Smuzhiyun #define CCM_CCR_BOOTPS_32 (0x0000) 211*4882a593Smuzhiyun #define CCM_CCR_BOOTPS_16 (0x0020) 212*4882a593Smuzhiyun #define CCM_CCR_BOOTPS_8 (0x0010) 213*4882a593Smuzhiyun #define CCM_CCR_BOOTPS_ (0x0000) 214*4882a593Smuzhiyun #define CCM_CCR_ALESEL (0x0008) 215*4882a593Smuzhiyun #define CCM_CCR_OSCMOD (0x0004) 216*4882a593Smuzhiyun #define CCM_CCR_PLLMOD (0x0002) 217*4882a593Smuzhiyun #define CCM_CCR_BOOTMEM (0x0001) 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun #define CCM_CIR_PIN_MASK (0xFFC0) 220*4882a593Smuzhiyun #define CCM_CIR_PRN_MASK (0x003F) 221*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54410 (0x9F<<6) 222*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54415 (0xA0<<6) 223*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54416 (0xA1<<6) 224*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54417 (0xA2<<6) 225*4882a593Smuzhiyun #define CCM_CIR_PIN_MCF54418 (0xA3<<6) 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun #define CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14) 228*4882a593Smuzhiyun #define CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF) 229*4882a593Smuzhiyun #define CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000) 230*4882a593Smuzhiyun #define CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000) 231*4882a593Smuzhiyun #define CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000) 232*4882a593Smuzhiyun #define CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000) 233*4882a593Smuzhiyun #define CCM_MISCCR_LIMP (0x1000) 234*4882a593Smuzhiyun #define CCM_MISCCR_BME (0x0800) 235*4882a593Smuzhiyun #define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) 236*4882a593Smuzhiyun #define CCM_MISCCR_BMT_65536 (0) 237*4882a593Smuzhiyun #define CCM_MISCCR_BMT_32768 (1) 238*4882a593Smuzhiyun #define CCM_MISCCR_BMT_16384 (2) 239*4882a593Smuzhiyun #define CCM_MISCCR_BMT_8192 (3) 240*4882a593Smuzhiyun #define CCM_MISCCR_BMT_4096 (4) 241*4882a593Smuzhiyun #define CCM_MISCCR_BMT_2048 (5) 242*4882a593Smuzhiyun #define CCM_MISCCR_BMT_1024 (6) 243*4882a593Smuzhiyun #define CCM_MISCCR_BMT_512 (7) 244*4882a593Smuzhiyun #define CCM_MISCCR_SDHCSRC (0x0040) 245*4882a593Smuzhiyun #define CCM_MISCCR_SSI1SRC (0x0020) 246*4882a593Smuzhiyun #define CCM_MISCCR_SSI0SRC (0x0010) 247*4882a593Smuzhiyun #define CCM_MISCCR_USBHOC (0x0008) 248*4882a593Smuzhiyun #define CCM_MISCCR_USBOOC (0x0004) 249*4882a593Smuzhiyun #define CCM_MISCCR_USBPUE (0x0002) 250*4882a593Smuzhiyun #define CCM_MISCCR_USBSRC (0x0001) 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #define CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8) 253*4882a593Smuzhiyun #define CCM_CDRH_SSI0DIV_MASK (0x00FF) 254*4882a593Smuzhiyun #define CCM_CDRH_SSI1DIV(x) (((x)&0x00FF)) 255*4882a593Smuzhiyun #define CCM_CDRH_SSI1DIV_MASK (0xFF00) 256*4882a593Smuzhiyun #define CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8) 257*4882a593Smuzhiyun #define CCM_CDRL_LPDIV_MASK (0xFF0F) 258*4882a593Smuzhiyun #define CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x) 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun #define CCM_UOCSR_DPPD (0x2000) 261*4882a593Smuzhiyun #define CCM_UOCSR_DMPD (0x1000) 262*4882a593Smuzhiyun #define CCM_UOCSR_DRV_VBUS (0x0800) 263*4882a593Smuzhiyun #define CCM_UOCSR_CRG_VBUS (0x0400) 264*4882a593Smuzhiyun #define CCM_UOCSR_DCR_VBUS (0x0200) 265*4882a593Smuzhiyun #define CCM_UOCSR_DPPU (0x0100) 266*4882a593Smuzhiyun #define CCM_UOCSR_AVLD (0x0080) 267*4882a593Smuzhiyun #define CCM_UOCSR_BVLD (0x0040) 268*4882a593Smuzhiyun #define CCM_UOCSR_VVLD (0x0020) 269*4882a593Smuzhiyun #define CCM_UOCSR_SEND (0x0010) 270*4882a593Smuzhiyun #define CCM_UOCSR_PWRFLT (0x0008) 271*4882a593Smuzhiyun #define CCM_UOCSR_WKUP (0x0004) 272*4882a593Smuzhiyun #define CCM_UOCSR_UOMIE (0x0002) 273*4882a593Smuzhiyun #define CCM_UOCSR_XPDE (0x0001) 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #define CCM_UHCSR_DRV_VBUS (0x0010) 276*4882a593Smuzhiyun #define CCM_UHCSR_PWRFLT (0x0008) 277*4882a593Smuzhiyun #define CCM_UHCSR_WKUP (0x0004) 278*4882a593Smuzhiyun #define CCM_UHCSR_UOMIE (0x0002) 279*4882a593Smuzhiyun #define CCM_UHCSR_XPDE (0x0001) 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun #define CCM_MISCCR3_TMR_ENET (0x1000) 282*4882a593Smuzhiyun #define CCM_MISCCR3_ENETCLK(x) (((x)&7)<<8) 283*4882a593Smuzhiyun #define CCM_MISCCR3_ENETCLK_MASK (0xF8FF) 284*4882a593Smuzhiyun #define CCM_MISCCR3_ENETCLK_MII (0x0700) 285*4882a593Smuzhiyun #define CCM_MISCCR3_ENETCLK_OSC (0x0600) 286*4882a593Smuzhiyun #define CCM_MISCCR3_ENETCLK_USB (0x0500) 287*4882a593Smuzhiyun #define CCM_MISCCR3_ENETCLK_TMR3 (0x0400) 288*4882a593Smuzhiyun #define CCM_MISCCR3_ENETCLK_TMR2 (0x0300) 289*4882a593Smuzhiyun #define CCM_MISCCR3_ENETCLK_TMR1 (0x0200) 290*4882a593Smuzhiyun #define CCM_MISCCR3_ENETCLK_TMR0 (0x0100) 291*4882a593Smuzhiyun #define CCM_MISCCR3_ENETCLK_INTBUS (0x0000) 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun #define CCM_MISCCR2_EXTCLKBYP (0x8000) 294*4882a593Smuzhiyun #define CCM_MISCCR2_DDR2CLK (0x4000) 295*4882a593Smuzhiyun #define CCM_MISCCR2_RGPIO_HALF (0x2000) 296*4882a593Smuzhiyun #define CCM_MISCCR2_SWTSCR (0x1000) 297*4882a593Smuzhiyun #define CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8) 298*4882a593Smuzhiyun #define CCM_MISCCR2_PLLMODE_MASK (0xF8FF) 299*4882a593Smuzhiyun #define CCM_MISCCR2_DCCBYP (0x0080) 300*4882a593Smuzhiyun #define CCM_MISCCR2_DAC1SEL (0x0040) 301*4882a593Smuzhiyun #define CCM_MISCCR2_DAC0SEL (0x0020) 302*4882a593Smuzhiyun #define CCM_MISCCR2_ADCEN (0x0010) 303*4882a593Smuzhiyun #define CCM_MISCCR2_ADC7SEL (0x0008) 304*4882a593Smuzhiyun #define CCM_MISCCR2_ADC3SEL (0x0004) 305*4882a593Smuzhiyun #define CCM_MISCCR2_FBHALF (0x0002) 306*4882a593Smuzhiyun #define CCM_MISCCR2_ULPI (0x0001) 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun #define CCM_FNACR_PCR(x) (((x)&0x0F)<<24) 309*4882a593Smuzhiyun #define CCM_FNACR_PCR_MASK (0xF0FFFFFF) 310*4882a593Smuzhiyun #define CCM_FNACR_MCC(x) ((x)&0xFFFF) 311*4882a593Smuzhiyun #define CCM_FNACR_MCC_MASK (0xFFFF0000) 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun /* General Purpose I/O Module (GPIO) */ 314*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6) 315*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_ALE_MASK (0x3F) 316*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0) 317*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_ALE_FB_TS (0x80) 318*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_ALE_GPIO (0x00) 319*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4) 320*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_OE_MASK (0xCF) 321*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_OE_FB_OE (0x30) 322*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_OE_FB_TBST (0x20) 323*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_OE_NFC_RE (0x20) 324*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_OE_GPIO (0x00) 325*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_FBCLK (0x08) 326*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_RW (0x04) 327*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TA(x) ((x)&3) 328*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TA_MASK (0xFC) 329*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TA_TA (0x03) 330*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TA_NFC_RB (0x01) 331*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TA_GPIO (0x00) 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) 334*4882a593Smuzhiyun #define GPIO_PAR_BE_BE3_MASK (0x3F) 335*4882a593Smuzhiyun #define GPIO_PAR_BE_BE3_BE3 (0xC0) 336*4882a593Smuzhiyun #define GPIO_PAR_BE_BE3_CS3 (0x80) 337*4882a593Smuzhiyun #define GPIO_PAR_BE_BE3_FB_A1 (0x40) 338*4882a593Smuzhiyun #define GPIO_PAR_BE_BE3_NFC_ALE (0x40) 339*4882a593Smuzhiyun #define GPIO_PAR_BE_BE3_GPIO (0x00) 340*4882a593Smuzhiyun #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) 341*4882a593Smuzhiyun #define GPIO_PAR_BE_BE2_MASK (0xCF) 342*4882a593Smuzhiyun #define GPIO_PAR_BE_BE2_BE2 (0x30) 343*4882a593Smuzhiyun #define GPIO_PAR_BE_BE2_CS2 (0x20) 344*4882a593Smuzhiyun #define GPIO_PAR_BE_BE2_FB_A0 (0x10) 345*4882a593Smuzhiyun #define GPIO_PAR_BE_BE2_NFC_CLE (0x10) 346*4882a593Smuzhiyun #define GPIO_PAR_BE_BE2_GPIO (0x00) 347*4882a593Smuzhiyun #define GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2) 348*4882a593Smuzhiyun #define GPIO_PAR_BE_BE1_MASK (0xF3) 349*4882a593Smuzhiyun #define GPIO_PAR_BE_BE1_BE1 (0x0C) 350*4882a593Smuzhiyun #define GPIO_PAR_BE_BE1_FB_TSZ1 (0x08) 351*4882a593Smuzhiyun #define GPIO_PAR_BE_BE1_GPIO (0x00) 352*4882a593Smuzhiyun #define GPIO_PAR_BE_BS0(x) ((x)&0x03) 353*4882a593Smuzhiyun #define GPIO_PAR_BE_BE0_MASK (0xFC) 354*4882a593Smuzhiyun #define GPIO_PAR_BE_BE0_BE0 (0x03) 355*4882a593Smuzhiyun #define GPIO_PAR_BE_BE0_FB_TSZ0 (0x02) 356*4882a593Smuzhiyun #define GPIO_PAR_BE_BE0_GPIO (0x00) 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun #define GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6) 359*4882a593Smuzhiyun #define GPIO_PAR_CS_CS5_MASK (0x3F) 360*4882a593Smuzhiyun #define GPIO_PAR_CS_CS5_CS5 (0xC0) 361*4882a593Smuzhiyun #define GPIO_PAR_CS_CS5_DACK1 (0x80) 362*4882a593Smuzhiyun #define GPIO_PAR_CS_CS5_GPIO (0x00) 363*4882a593Smuzhiyun #define GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4) 364*4882a593Smuzhiyun #define GPIO_PAR_CS_CS4_MASK (0xCF) 365*4882a593Smuzhiyun #define GPIO_PAR_CS_CS4_CS4 (0x30) 366*4882a593Smuzhiyun #define GPIO_PAR_CS_CS4_DREQ1 (0x20) 367*4882a593Smuzhiyun #define GPIO_PAR_CS_CS4_GPIO (0x00) 368*4882a593Smuzhiyun #define GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2) 369*4882a593Smuzhiyun #define GPIO_PAR_CS_CS1_MASK (0xF3) 370*4882a593Smuzhiyun #define GPIO_PAR_CS_CS1_CS1 (0x0C) 371*4882a593Smuzhiyun #define GPIO_PAR_CS_CS1_NFC_CE (0x04) 372*4882a593Smuzhiyun #define GPIO_PAR_CS_CS1_GPIO (0x00) 373*4882a593Smuzhiyun #define GPIO_PAR_CS_CS0_CS0 (0x01) 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6) 376*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F) 377*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0) 378*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80) 379*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40) 380*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00) 381*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4) 382*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF) 383*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30) 384*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20) 385*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10) 386*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00) 387*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2) 388*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3) 389*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C) 390*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08) 391*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04) 392*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00) 393*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03) 394*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC) 395*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03) 396*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02) 397*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01) 398*4882a593Smuzhiyun #define GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00) 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun #define GPIO_PAR_IRQH_IRQ7 (0x10) 401*4882a593Smuzhiyun #define GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2) 402*4882a593Smuzhiyun #define GPIO_PAR_IRQH_IRQ4_MASK (0xF3) 403*4882a593Smuzhiyun #define GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C) 404*4882a593Smuzhiyun #define GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08) 405*4882a593Smuzhiyun #define GPIO_PAR_IRQH_IRQ4_GPIO (0x00) 406*4882a593Smuzhiyun #define GPIO_PAR_IRQH_IRQ1 (0x03) 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6) 409*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ6_MASK (0x3F) 410*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0) 411*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40) 412*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ6_GPIO (0x00) 413*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4) 414*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ3_MASK (0xCF) 415*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30) 416*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20) 417*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10) 418*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ3_GPIO (0x00) 419*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2) 420*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ2_MASK (0xF3) 421*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C) 422*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08) 423*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04) 424*4882a593Smuzhiyun #define GPIO_PAR_IRQL_IRQ2_GPIO (0x00) 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6) 427*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SIN_MASK (0x3F) 428*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0) 429*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0) 430*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SIN_U3RXD (0x80) 431*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40) 432*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SIN_GPIO (0x00) 433*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4) 434*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SOUT_MASK (0xCF) 435*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30) 436*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30) 437*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SOUT_U3TXD (0x20) 438*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10) 439*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SOUT_GPIO (0x00) 440*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2) 441*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SCK_MASK (0xF3) 442*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C) 443*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C) 444*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08) 445*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04) 446*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_SCK_GPIO (0x00) 447*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03) 448*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_PCS0_MASK (0xFC) 449*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03) 450*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_PCS0_SS (0x03) 451*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02) 452*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01) 453*4882a593Smuzhiyun #define GPIO_PAR_DSPI0_PCS0_GPIO (0x00) 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun #define GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80) 456*4882a593Smuzhiyun #define GPIO_PAR_DSPIOW_SBF_CS (0x80) 457*4882a593Smuzhiyun #define GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4) 458*4882a593Smuzhiyun #define GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF) 459*4882a593Smuzhiyun #define GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30) 460*4882a593Smuzhiyun #define GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20) 461*4882a593Smuzhiyun #define GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00) 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) 464*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_MASK (0x3F) 465*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) 466*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0) 467*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) 468*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40) 469*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_ULIPI_DIR (0x40) 470*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) 471*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) 472*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_MASK (0xCF) 473*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) 474*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_EXTA2 (0x30) 475*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) 476*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10) 477*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) 478*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) 479*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_MASK (0xF3) 480*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) 481*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C) 482*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) 483*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04) 484*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) 485*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN(x) ((x)&0x03) 486*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_MASK (0xFC) 487*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) 488*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_EXTA0 (0x03) 489*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) 490*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01) 491*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01) 492*4882a593Smuzhiyun #define GPIO_PAR_TIMER_T0IN_GPIO (0x00) 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6) 495*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2CTS_MASK (0x3F) 496*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2CTS_U2CTS (0xC0) 497*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2CTS_U6TXD (0x80) 498*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40) 499*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2CTS_GPIO (0x00) 500*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4) 501*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RTS_MASK (0xCF) 502*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RTS_U2RTS (0x30) 503*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RTS_U6RXD (0x20) 504*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10) 505*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RTS_GPIO (0x00) 506*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2) 507*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RXD_MASK (0xF3) 508*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RXD_U2RXD (0x0C) 509*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08) 510*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04) 511*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2RXD_GPIO (0x00) 512*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2TXD(x) ((x)&0x03) 513*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2TXD_MASK (0xFC) 514*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2TXD_U2TXD (0x03) 515*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02) 516*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01) 517*4882a593Smuzhiyun #define GPIO_PAR_UART2_U2TXD_GPIO (0x00) 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6) 520*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1CTS_MASK (0x3F) 521*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1CTS_U1CTS (0xC0) 522*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1CTS_U5TXD (0x80) 523*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40) 524*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1CTS_GPIO (0x00) 525*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4) 526*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RTS_MASK (0xCF) 527*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RTS_U1RTS (0x30) 528*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RTS_U5RXD (0x20) 529*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10) 530*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RTS_GPIO (0x00) 531*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2) 532*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RXD_MASK (0xF3) 533*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RXD_U1RXD (0x0C) 534*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08) 535*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04) 536*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1RXD_GPIO (0x00) 537*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1TXD(x) ((x)&0x03) 538*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1TXD_MASK (0xFC) 539*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1TXD_U1TXD (0x03) 540*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02) 541*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01) 542*4882a593Smuzhiyun #define GPIO_PAR_UART1_U1TXD_GPIO (0x00) 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6) 545*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0CTS_MASK (0x3F) 546*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0CTS_U0CTS (0xC0) 547*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0CTS_U4TXD (0x80) 548*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40) 549*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0CTS_GPIO (0x00) 550*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4) 551*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RTS_MASK (0xCF) 552*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RTS_U0RTS (0x30) 553*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RTS_U4RXD (0x20) 554*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10) 555*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RTS_GPIO (0x00) 556*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2) 557*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RXD_MASK (0xF3) 558*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RXD_U0RXD (0x0C) 559*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08) 560*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04) 561*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0RXD_GPIO (0x00) 562*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0TXD(x) ((x)&0x03) 563*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0TXD_MASK (0xFC) 564*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0TXD_U0TXD (0x03) 565*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02) 566*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01) 567*4882a593Smuzhiyun #define GPIO_PAR_UART0_U0TXD_GPIO (0x00) 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6) 570*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT3_MASK (0x3F) 571*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0) 572*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80) 573*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40) 574*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT3_GPIO (0x00) 575*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4) 576*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT2_MASK (0xCF) 577*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT2_DAT2 (0x30) 578*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20) 579*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10) 580*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT2_GPIO (0x00) 581*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2) 582*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT1_MASK (0xF3) 583*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C) 584*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08) 585*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04) 586*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT1_GPIO (0x00) 587*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03) 588*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT0_MASK (0xFC) 589*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT0_DAT0 (0x03) 590*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02) 591*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01) 592*4882a593Smuzhiyun #define GPIO_PAR_SDHCH_DAT0_GPIO (0x00) 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2) 595*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CMD_MASK (0xF3) 596*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CMD_CMD (0x0C) 597*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08) 598*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04) 599*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CMD_GPIO (0x00) 600*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CLK(x) ((x)&0x03) 601*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CLK_MASK (0xFC) 602*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CLK_CLK (0x03) 603*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02) 604*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01) 605*4882a593Smuzhiyun #define GPIO_PAR_SDHCL_CLK_GPIO (0x00) 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6) 608*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_DAT_MASK (0x3F) 609*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_DAT_DAT (0xC0) 610*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80) 611*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40) 612*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_DAT_GPIO (0x00) 613*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4) 614*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_VEN_MASK (0xCF) 615*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_VEN_VEN (0x30) 616*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20) 617*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_VEN_GPIO (0x00) 618*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2) 619*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_RST_MASK (0xF3) 620*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_RST_RST (0x0C) 621*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08) 622*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04) 623*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_RST_GPIO (0x00) 624*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_PD(x) ((x)&0x03) 625*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_PD_MASK (0xFC) 626*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_PD_PD (0x03) 627*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02) 628*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01) 629*4882a593Smuzhiyun #define GPIO_PAR_SIMP0H_PD_GPIO (0x00) 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun #define GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03) 632*4882a593Smuzhiyun #define GPIO_PAR_SIMP0L_CLK_MASK (0xFC) 633*4882a593Smuzhiyun #define GPIO_PAR_SIMP0L_CLK_CLK (0x03) 634*4882a593Smuzhiyun #define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02) 635*4882a593Smuzhiyun #define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01) 636*4882a593Smuzhiyun #define GPIO_PAR_SIMP0L_CLK_GPIO (0x00) 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6) 639*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_RXD_MASK (0x3F) 640*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_RXD_RXD (0xC0) 641*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80) 642*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40) 643*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_RXD_GPIO (0x00) 644*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4) 645*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_TXD_MASK (0xCF) 646*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_TXD_TXD (0x30) 647*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20) 648*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10) 649*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_TXD_GPIO (0x00) 650*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2) 651*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_FS_MASK (0xF3) 652*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_FS_FS (0x0C) 653*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_FS_U7TXD (0x08) 654*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_FS_SIM1_RST (0x04) 655*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_FS_GPIO (0x00) 656*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03) 657*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_MCLK_MASK (0xFC) 658*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_MCLK_MCLK (0x03) 659*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02) 660*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01) 661*4882a593Smuzhiyun #define GPIO_PAR_SSI0H_MCLK_GPIO (0x00) 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun #define GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03) 664*4882a593Smuzhiyun #define GPIO_PAR_SSI0L_BCLK_MASK (0xFC) 665*4882a593Smuzhiyun #define GPIO_PAR_SSI0L_BCLK_BCLK (0x03) 666*4882a593Smuzhiyun #define GPIO_PAR_SSI0L_BCLK_U7RXD (0x02) 667*4882a593Smuzhiyun #define GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01) 668*4882a593Smuzhiyun #define GPIO_PAR_SSI0L_BCLK_GPIO (0x00) 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun #define GPIO_PAR_DEBUGH1_DAT3 (0x40) 671*4882a593Smuzhiyun #define GPIO_PAR_DEBUGH1_DAT2 (0x10) 672*4882a593Smuzhiyun #define GPIO_PAR_DEBUGH1_DAT1 (0x04) 673*4882a593Smuzhiyun #define GPIO_PAR_DEBUGH1_DAT0 (0x01) 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun #define GPIO_PAR_DEBUGH0_PST3 (0x40) 676*4882a593Smuzhiyun #define GPIO_PAR_DEBUGH0_PST2 (0x10) 677*4882a593Smuzhiyun #define GPIO_PAR_DEBUGH0_PST1 (0x04) 678*4882a593Smuzhiyun #define GPIO_PAR_DEBUGH0_PST0 (0x01) 679*4882a593Smuzhiyun 680*4882a593Smuzhiyun #define GPIO_PODR_G4_VAL (0x01 << 4) 681*4882a593Smuzhiyun #define GPIO_PODR_G4_MASK (0xff & ~GPIO_PODR_G4_VAL) 682*4882a593Smuzhiyun #define GPIO_PDDR_G4_OUTPUT (0x01 << 4) 683*4882a593Smuzhiyun #define GPIO_PDDR_G4_MASK (0xff & ~GPIO_PDDR_G4_OUTPUT) 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun #define GPIO_PAR_DEBUGL_ALLPST (0x01) 686*4882a593Smuzhiyun 687*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC(x) ((x)&0x0F) 688*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_MASK (0xF0) 689*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_GPIO (0x0D) 690*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_RMII1 (0x0C) 691*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_RMII1FUL (0x0B) 692*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A) 693*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_RMII0 (0x09) 694*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08) 695*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_RMII0FUL (0x07) 696*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06) 697*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */ 698*4882a593Smuzhiyun /* Both 0&1: MDC, MDIO, COL & TXER - GPIO */ 699*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_RMII0_1 (0x04) 700*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03) 701*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */ 702*4882a593Smuzhiyun #define GPIO_PAR_FEC_FEC_MIIFUL (0x00) 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun 705*4882a593Smuzhiyun /* TC: Need to edit here.... */ 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun /* Mode Select Control */ 708*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_MSC(x) ((x)&0x03) 709*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_MSC_MASK (0xFC) 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun /* Slew Rate Control */ 712*4882a593Smuzhiyun 713*4882a593Smuzhiyun #define GPIO_SRCR_FB3_FB3(x) ((x)&0x03) 714*4882a593Smuzhiyun #define GPIO_SRCR_FB3_FB3_MASK (0xFC) 715*4882a593Smuzhiyun 716*4882a593Smuzhiyun #define GPIO_SRCR_FB2_FB2(x) ((x)&0x03) 717*4882a593Smuzhiyun #define GPIO_SRCR_FB2_FB2_MASK (0xFC) 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun #define GPIO_SRCR_FB1_FB1(x) ((x)&0x03) 720*4882a593Smuzhiyun #define GPIO_SRCR_FB1_FB1_MASK (0xFC) 721*4882a593Smuzhiyun 722*4882a593Smuzhiyun #define GPIO_SRCR_FB4_FB5(x) (((x)&0x03)<<2) 723*4882a593Smuzhiyun #define GPIO_SRCR_FB4_FB5_MASK (0xF3) 724*4882a593Smuzhiyun #define GPIO_SRCR_FB4_FB4(x) ((x)&0x03) 725*4882a593Smuzhiyun #define GPIO_SRCR_FB4_FB4_MASK (0xFC) 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun #define GPIO_SRCR_DSPIOW_OWDAT(x) (((x)&0x03)<<4) 728*4882a593Smuzhiyun #define GPIO_SRCR_DSPIOW_OWDAT_MASK (0xCF) 729*4882a593Smuzhiyun #define GPIO_SRCR_DSPIOW_DSPI0(x) ((x)&0x03) 730*4882a593Smuzhiyun #define GPIO_SRCR_DSPIOW_DSPI0_MASK (0xFC) 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun #define GPIO_SRCR_CANI2C_CAN1(x) (((x)&0x03)<<2) 733*4882a593Smuzhiyun #define GPIO_SRCR_CANI2C_CAN1_MASK (0xF3) 734*4882a593Smuzhiyun #define GPIO_SRCR_CANI2C_I2C0(x) ((x)&0x03) 735*4882a593Smuzhiyun #define GPIO_SRCR_CANI2C_I2C0_MASK (0xFC) 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun #define GPIO_SRCR_IRQ0_IRQ0(x) ((x)&0x03) 738*4882a593Smuzhiyun #define GPIO_SRCR_IRQ0_IRQ0_MASK (0xFC) 739*4882a593Smuzhiyun 740*4882a593Smuzhiyun #define GPIO_SRCR_TIMER_TMR3(x) (((x)&0x03)<<6) 741*4882a593Smuzhiyun #define GPIO_SRCR_TIMER_TMR3_MASK (0x3F) 742*4882a593Smuzhiyun #define GPIO_SRCR_TIMER_TMR2(x) (((x)&0x03)<<4) 743*4882a593Smuzhiyun #define GPIO_SRCR_TIMER_TMR2_MASK (0xCF) 744*4882a593Smuzhiyun #define GPIO_SRCR_TIMER_TMR1(x) (((x)&0x03)<<2) 745*4882a593Smuzhiyun #define GPIO_SRCR_TIMER_TMR1_MASK (0xF3) 746*4882a593Smuzhiyun #define GPIO_SRCR_TIMER_TMR0(x) ((x)&0x03) 747*4882a593Smuzhiyun #define GPIO_SRCR_TIMER_TMR0_MASK (0xFC) 748*4882a593Smuzhiyun 749*4882a593Smuzhiyun #define GPIO_SRCR_UART_U2(x) (((x)&0x03)<<4) 750*4882a593Smuzhiyun #define GPIO_SRCR_UART_U2_MASK (0xCF) 751*4882a593Smuzhiyun #define GPIO_SRCR_UART_U1(x) (((x)&0x03)<<2) 752*4882a593Smuzhiyun #define GPIO_SRCR_UART_U1_MASK (0xF3) 753*4882a593Smuzhiyun #define GPIO_SRCR_UART_U0(x) ((x)&0x03) 754*4882a593Smuzhiyun #define GPIO_SRCR_UART_U0_MASK (0xFC) 755*4882a593Smuzhiyun 756*4882a593Smuzhiyun #define GPIO_SRCR_FEC_RMII0(x) (((x)&0x03)<<2) 757*4882a593Smuzhiyun #define GPIO_SRCR_FEC_RMII0_MASK (0xF3) 758*4882a593Smuzhiyun #define GPIO_SRCR_FEC_RMII1(x) ((x)&0x03) 759*4882a593Smuzhiyun #define GPIO_SRCR_FEC_RMII1_MASK (0xFC) 760*4882a593Smuzhiyun 761*4882a593Smuzhiyun #define GPIO_SRCR_SDHC_SDHC(x) ((x)&0x03) 762*4882a593Smuzhiyun #define GPIO_SRCR_SDHC_SDHC_MASK (0xFC) 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun #define GPIO_SRCR_SIM0_SIMP0(x) ((x)&0x03) 765*4882a593Smuzhiyun #define GPIO_SRCR_SIM0_SIMP0_MASK (0xFC) 766*4882a593Smuzhiyun 767*4882a593Smuzhiyun #define GPIO_SRCR_SSI0_SSI0(x) ((x)&0x03) 768*4882a593Smuzhiyun #define GPIO_SRCR_SSI0_SSI0_MASK (0xFC) 769*4882a593Smuzhiyun 770*4882a593Smuzhiyun #define GPIO_PCR_URTS_U2 (0x0004) 771*4882a593Smuzhiyun #define GPIO_PCR_URTS_U1 (0x0002) 772*4882a593Smuzhiyun #define GPIO_PCR_URTS_U0 (0x0001) 773*4882a593Smuzhiyun 774*4882a593Smuzhiyun #define GPIO_PCR_UCTS_U2 (0x0004) 775*4882a593Smuzhiyun #define GPIO_PCR_UCTS_U1 (0x0002) 776*4882a593Smuzhiyun #define GPIO_PCR_UCTS_U0 (0x0001) 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun #define GPIO_UTXD_WOM_U9 (0x0200) 779*4882a593Smuzhiyun #define GPIO_UTXD_WOM_U8 (0x0100) 780*4882a593Smuzhiyun #define GPIO_UTXD_WOM_U7 (0x0080) 781*4882a593Smuzhiyun #define GPIO_UTXD_WOM_U6 (0x0040) 782*4882a593Smuzhiyun #define GPIO_UTXD_WOM_U5 (0x0020) 783*4882a593Smuzhiyun #define GPIO_UTXD_WOM_U4 (0x0010) 784*4882a593Smuzhiyun #define GPIO_UTXD_WOM_U3 (0x0008) 785*4882a593Smuzhiyun #define GPIO_UTXD_WOM_U2 (0x0004) 786*4882a593Smuzhiyun #define GPIO_UTXD_WOM_U1 (0x0002) 787*4882a593Smuzhiyun #define GPIO_UTXD_WOM_U0 (0x0001) 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun #define GPIO_URXD_WOM_U9(x) (((x)&3)<<18) 790*4882a593Smuzhiyun #define GPIO_URXD_WOM_U9_MASK (0xFFF3FFFF) 791*4882a593Smuzhiyun #define GPIO_URXD_WOM_U8(x) (((x)&3)<<16) 792*4882a593Smuzhiyun #define GPIO_URXD_WOM_U8_MASK (0xFFFCFFFF) 793*4882a593Smuzhiyun #define GPIO_URXD_WOM_U7(x) (((x)&3)<<14) 794*4882a593Smuzhiyun #define GPIO_URXD_WOM_U7_MASK (0xFFFF3FFF) 795*4882a593Smuzhiyun #define GPIO_URXD_WOM_U6(x) (((x)&3)<<12) 796*4882a593Smuzhiyun #define GPIO_URXD_WOM_U6_MASK (0xFFFFCFFF) 797*4882a593Smuzhiyun #define GPIO_URXD_WOM_U5(x) (((x)&3)<<10) 798*4882a593Smuzhiyun #define GPIO_URXD_WOM_U5_MASK (0xFFFFF3FF) 799*4882a593Smuzhiyun #define GPIO_URXD_WOM_U4(x) (((x)&3)<<8) 800*4882a593Smuzhiyun #define GPIO_URXD_WOM_U4_MASK (0xFFFFFCFF) 801*4882a593Smuzhiyun #define GPIO_URXD_WOM_U3(x) (((x)&3)<<6) 802*4882a593Smuzhiyun #define GPIO_URXD_WOM_U3_MASK (0xFFFFFF3F) 803*4882a593Smuzhiyun #define GPIO_URXD_WOM_U2(x) (((x)&3)<<4) 804*4882a593Smuzhiyun #define GPIO_URXD_WOM_U2_MASK (0xFFFFFFCF) 805*4882a593Smuzhiyun #define GPIO_URXD_WOM_U1(x) (((x)&3)<<2) 806*4882a593Smuzhiyun #define GPIO_URXD_WOM_U1_MASK (0xFFFFFFF3) 807*4882a593Smuzhiyun #define GPIO_URXD_WOM_U0(x) ((x)&3) 808*4882a593Smuzhiyun #define GPIO_URXD_WOM_U0_MASK (0xFFFFFFFC) 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun #define GPIO_HCR1_PG4_0(x) (((x)&0x1F)<<27) 811*4882a593Smuzhiyun #define GPIO_HCR1_PG4_0_MASK (0x07FFFFFF) 812*4882a593Smuzhiyun #define GPIO_HCR1_PF7_3(x) (((x)&0x1F)<<22) 813*4882a593Smuzhiyun #define GPIO_HCR1_PF7_3_MASK (0xF83FFFFF) 814*4882a593Smuzhiyun #define GPIO_HCR1_PE6_0(x) (((x)&0x7F)<<15) 815*4882a593Smuzhiyun #define GPIO_HCR1_PE6_0_MASK (0xFFC07FFF) 816*4882a593Smuzhiyun #define GPIO_HCR1_PD7_3(x) (((x)&0x1F)<<10) 817*4882a593Smuzhiyun #define GPIO_HCR1_PD7_3_MASK (0xFFFF83FF) 818*4882a593Smuzhiyun #define GPIO_HCR1_PC7_1(x) (((x)&0x7F)<<3) 819*4882a593Smuzhiyun #define GPIO_HCR1_PC7_1_MASK (0xFFFFFC07) 820*4882a593Smuzhiyun #define GPIO_HCR1_PB2_0(x) ((x)&7) 821*4882a593Smuzhiyun #define GPIO_HCR1_PB2_0_MASK (0xFFFFFFF8) 822*4882a593Smuzhiyun 823*4882a593Smuzhiyun #define GPIO_HCR0_PK3 (0x00000400) 824*4882a593Smuzhiyun #define GPIO_HCR0_PK0 (0x00000200) 825*4882a593Smuzhiyun #define GPIO_HCR0_PD2_0(x) (((x)&7)<<6) 826*4882a593Smuzhiyun #define GPIO_HCR0_PD2_0_MASK (0xFFFFFE3F) 827*4882a593Smuzhiyun #define GPIO_HCR0_PE7 (0x00000020) 828*4882a593Smuzhiyun #define GPIO_HCR0_PH7_3(x) ((x)&0x1F) 829*4882a593Smuzhiyun #define GPIO_HCR0_PH7_3_MASK(x) (0xFFFFFFE0) 830*4882a593Smuzhiyun 831*4882a593Smuzhiyun /* SDRAM Controller (SDRAMC) */ 832*4882a593Smuzhiyun 833*4882a593Smuzhiyun /* Phase Locked Loop (PLL) */ 834*4882a593Smuzhiyun #define PLL_CR_LOCIRQ (0x00040000) 835*4882a593Smuzhiyun #define PLL_CR_LOCRE (0x00020000) 836*4882a593Smuzhiyun #define PLL_CR_LOCEN (0x00010000) 837*4882a593Smuzhiyun #define PLL_CR_LOLIRQ (0x00004000) 838*4882a593Smuzhiyun #define PLL_CR_LOLRE (0x00002000) 839*4882a593Smuzhiyun #define PLL_CR_LOLEN (0x00001000) 840*4882a593Smuzhiyun #define PLL_CR_REFDIV(x) (((x)&7)<<8) 841*4882a593Smuzhiyun #define PLL_CR_REFDIV_MASK (0xFFFFF8FF) 842*4882a593Smuzhiyun #define PLL_CR_FBKDIV(x) ((x)&0x3F) 843*4882a593Smuzhiyun #define PLL_CR_FBKDIV_MASK (0xFFFFFFC0) 844*4882a593Smuzhiyun #define PLL_CR_FBKDIV_BITS (0x3F) 845*4882a593Smuzhiyun 846*4882a593Smuzhiyun #define PLL_DR_OUTDIV5(x) (((x)&0x1F)<<21) 847*4882a593Smuzhiyun #define PLL_DR_OUTDIV5_MASK (0xFC1FFFFF) 848*4882a593Smuzhiyun #define PLL_DR_OUTDIV5_BITS (0x03E00000) 849*4882a593Smuzhiyun #define PLL_DR_OUTDIV4(x) (((x)&0x1F)<<16) 850*4882a593Smuzhiyun #define PLL_DR_OUTDIV4_MASK (0xFFE0FFFF) 851*4882a593Smuzhiyun #define PLL_DR_OUTDIV4_BITS (0x001F0000) 852*4882a593Smuzhiyun #define PLL_DR_OUTDIV3(x) (((x)&0x1F)<<10) 853*4882a593Smuzhiyun #define PLL_DR_OUTDIV3_MASK (0xFFFF83FF) 854*4882a593Smuzhiyun #define PLL_DR_OUTDIV3_BITS (0x00007C00) 855*4882a593Smuzhiyun #define PLL_DR_OUTDIV2(x) (((x)&0x1F)<<5) 856*4882a593Smuzhiyun #define PLL_DR_OUTDIV2_MASK (0xFFFFFC1F) 857*4882a593Smuzhiyun #define PLL_DR_OUTDIV2_BITS (0x000003E0) 858*4882a593Smuzhiyun #define PLL_DR_OUTDIV1(x) ((x)&0x1F) 859*4882a593Smuzhiyun #define PLL_DR_OUTDIV1_MASK (0xFFFFFFE0) 860*4882a593Smuzhiyun #define PLL_DR_OUTDIV1_BITS (0x0000001F) 861*4882a593Smuzhiyun 862*4882a593Smuzhiyun #define PLL_SR_LOCF (0x00000200) 863*4882a593Smuzhiyun #define PLL_SR_LOC (0x00000100) 864*4882a593Smuzhiyun #define PLL_SR_LOLF (0x00000040) 865*4882a593Smuzhiyun #define PLL_SR_LOCKS (0x00000020) 866*4882a593Smuzhiyun #define PLL_SR_LOCK (0x00000010) 867*4882a593Smuzhiyun #define PLL_PSR_LOCK PLL_SR_LOCK /* compatible with 5x */ 868*4882a593Smuzhiyun #define PLL_SR_MODE(x) ((x)&7) 869*4882a593Smuzhiyun #define PLL_SR_MODE_MASK (0xFFFFFFF8) 870*4882a593Smuzhiyun 871*4882a593Smuzhiyun #endif /* __MCF5441X__ */ 872