1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * mcf5329.h -- Definitions for Freescale Coldfire 5329 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef mcf5329_h 11*4882a593Smuzhiyun #define mcf5329_h 12*4882a593Smuzhiyun /****************************************************************************/ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /********************************************************************* 15*4882a593Smuzhiyun * System Control Module (SCM) 16*4882a593Smuzhiyun *********************************************************************/ 17*4882a593Smuzhiyun /* Bit definitions and macros for SCM_MPR */ 18*4882a593Smuzhiyun #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) 19*4882a593Smuzhiyun #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) 20*4882a593Smuzhiyun #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) 21*4882a593Smuzhiyun #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) 22*4882a593Smuzhiyun #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) 23*4882a593Smuzhiyun #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) 24*4882a593Smuzhiyun #define MPROT_MTR 4 25*4882a593Smuzhiyun #define MPROT_MTW 2 26*4882a593Smuzhiyun #define MPROT_MPL 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Bit definitions and macros for SCM_BMT */ 29*4882a593Smuzhiyun #define BMT_BME (0x08) 30*4882a593Smuzhiyun #define BMT_8 (0x07) 31*4882a593Smuzhiyun #define BMT_16 (0x06) 32*4882a593Smuzhiyun #define BMT_32 (0x05) 33*4882a593Smuzhiyun #define BMT_64 (0x04) 34*4882a593Smuzhiyun #define BMT_128 (0x03) 35*4882a593Smuzhiyun #define BMT_256 (0x02) 36*4882a593Smuzhiyun #define BMT_512 (0x01) 37*4882a593Smuzhiyun #define BMT_1024 (0x00) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Bit definitions and macros for SCM_PACRA */ 40*4882a593Smuzhiyun #define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28) 41*4882a593Smuzhiyun #define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24) 42*4882a593Smuzhiyun #define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20) 43*4882a593Smuzhiyun #define PACR_SP 4 44*4882a593Smuzhiyun #define PACR_WP 2 45*4882a593Smuzhiyun #define PACR_TP 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Bit definitions and macros for SCM_PACRB */ 48*4882a593Smuzhiyun #define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28) 49*4882a593Smuzhiyun #define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Bit definitions and macros for SCM_PACRC */ 52*4882a593Smuzhiyun #define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28) 53*4882a593Smuzhiyun #define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24) 54*4882a593Smuzhiyun #define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20) 55*4882a593Smuzhiyun #define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16) 56*4882a593Smuzhiyun #define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8) 57*4882a593Smuzhiyun #define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4) 58*4882a593Smuzhiyun #define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Bit definitions and macros for SCM_PACRD */ 61*4882a593Smuzhiyun #define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28) 62*4882a593Smuzhiyun #define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24) 63*4882a593Smuzhiyun #define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20) 64*4882a593Smuzhiyun #define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12) 65*4882a593Smuzhiyun #define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8) 66*4882a593Smuzhiyun #define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4) 67*4882a593Smuzhiyun #define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Bit definitions and macros for SCM_PACRE */ 70*4882a593Smuzhiyun #define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28) 71*4882a593Smuzhiyun #define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24) 72*4882a593Smuzhiyun #define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20) 73*4882a593Smuzhiyun #define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16) 74*4882a593Smuzhiyun #define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12) 75*4882a593Smuzhiyun #define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8) 76*4882a593Smuzhiyun #define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Bit definitions and macros for SCM_PACRF */ 79*4882a593Smuzhiyun #define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28) 80*4882a593Smuzhiyun #define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24) 81*4882a593Smuzhiyun #define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20) 82*4882a593Smuzhiyun #define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16) 83*4882a593Smuzhiyun #define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12) 84*4882a593Smuzhiyun #define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8) 85*4882a593Smuzhiyun #define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4) 86*4882a593Smuzhiyun #define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Bit definitions and macros for SCM_PACRG */ 89*4882a593Smuzhiyun #define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* Bit definitions and macros for SCM_PACRH */ 92*4882a593Smuzhiyun #define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28) 93*4882a593Smuzhiyun #define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24) 94*4882a593Smuzhiyun #define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* PACRn Assignments */ 97*4882a593Smuzhiyun #define PACR0(x) SCM_PACRA_PACR0(x) 98*4882a593Smuzhiyun #define PACR1(x) SCM_PACRA_PACR1(x) 99*4882a593Smuzhiyun #define PACR2(x) SCM_PACRA_PACR2(x) 100*4882a593Smuzhiyun #define PACR8(x) SCM_PACRB_PACR8(x) 101*4882a593Smuzhiyun #define PACR12(x) SCM_PACRB_PACR12(x) 102*4882a593Smuzhiyun #define PACR16(x) SCM_PACRC_PACR16(x) 103*4882a593Smuzhiyun #define PACR17(x) SCM_PACRC_PACR17(x) 104*4882a593Smuzhiyun #define PACR18(x) SCM_PACRC_PACR18(x) 105*4882a593Smuzhiyun #define PACR19(x) SCM_PACRC_PACR19(x) 106*4882a593Smuzhiyun #define PACR21(x) SCM_PACRC_PACR21(x) 107*4882a593Smuzhiyun #define PACR22(x) SCM_PACRC_PACR22(x) 108*4882a593Smuzhiyun #define PACR23(x) SCM_PACRC_PACR23(x) 109*4882a593Smuzhiyun #define PACR24(x) SCM_PACRD_PACR24(x) 110*4882a593Smuzhiyun #define PACR25(x) SCM_PACRD_PACR25(x) 111*4882a593Smuzhiyun #define PACR26(x) SCM_PACRD_PACR26(x) 112*4882a593Smuzhiyun #define PACR28(x) SCM_PACRD_PACR28(x) 113*4882a593Smuzhiyun #define PACR29(x) SCM_PACRD_PACR29(x) 114*4882a593Smuzhiyun #define PACR30(x) SCM_PACRD_PACR30(x) 115*4882a593Smuzhiyun #define PACR31(x) SCM_PACRD_PACR31(x) 116*4882a593Smuzhiyun #define PACR32(x) SCM_PACRE_PACR32(x) 117*4882a593Smuzhiyun #define PACR33(x) SCM_PACRE_PACR33(x) 118*4882a593Smuzhiyun #define PACR34(x) SCM_PACRE_PACR34(x) 119*4882a593Smuzhiyun #define PACR35(x) SCM_PACRE_PACR35(x) 120*4882a593Smuzhiyun #define PACR36(x) SCM_PACRE_PACR36(x) 121*4882a593Smuzhiyun #define PACR37(x) SCM_PACRE_PACR37(x) 122*4882a593Smuzhiyun #define PACR38(x) SCM_PACRE_PACR38(x) 123*4882a593Smuzhiyun #define PACR40(x) SCM_PACRF_PACR40(x) 124*4882a593Smuzhiyun #define PACR41(x) SCM_PACRF_PACR41(x) 125*4882a593Smuzhiyun #define PACR42(x) SCM_PACRF_PACR42(x) 126*4882a593Smuzhiyun #define PACR43(x) SCM_PACRF_PACR43(x) 127*4882a593Smuzhiyun #define PACR44(x) SCM_PACRF_PACR44(x) 128*4882a593Smuzhiyun #define PACR45(x) SCM_PACRF_PACR45(x) 129*4882a593Smuzhiyun #define PACR46(x) SCM_PACRF_PACR46(x) 130*4882a593Smuzhiyun #define PACR47(x) SCM_PACRF_PACR47(x) 131*4882a593Smuzhiyun #define PACR48(x) SCM_PACRG_PACR48(x) 132*4882a593Smuzhiyun #define PACR56(x) SCM_PACRH_PACR56(x) 133*4882a593Smuzhiyun #define PACR57(x) SCM_PACRH_PACR57(x) 134*4882a593Smuzhiyun #define PACR58(x) SCM_PACRH_PACR58(x) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Bit definitions and macros for SCM_CWCR */ 137*4882a593Smuzhiyun #define CWCR_RO (0x8000) 138*4882a593Smuzhiyun #define CWCR_CWR_WH (0x0100) 139*4882a593Smuzhiyun #define CWCR_CWE (0x0080) 140*4882a593Smuzhiyun #define CWRI_WINDOW (0x0060) 141*4882a593Smuzhiyun #define CWRI_RESET (0x0040) 142*4882a593Smuzhiyun #define CWRI_INT_RESET (0x0020) 143*4882a593Smuzhiyun #define CWRI_INT (0x0000) 144*4882a593Smuzhiyun #define CWCR_CWT(x) (((x)&0x001F)) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Bit definitions and macros for SCM_ISR */ 147*4882a593Smuzhiyun #define SCMISR_CFEI (0x02) 148*4882a593Smuzhiyun #define SCMISR_CWIC (0x01) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* Bit definitions and macros for SCM_BCR */ 151*4882a593Smuzhiyun #define BCR_GBR (0x00000200) 152*4882a593Smuzhiyun #define BCR_GBW (0x00000100) 153*4882a593Smuzhiyun #define BCR_S7 (0x00000080) 154*4882a593Smuzhiyun #define BCR_S6 (0x00000040) 155*4882a593Smuzhiyun #define BCR_S4 (0x00000010) 156*4882a593Smuzhiyun #define BCR_S1 (0x00000002) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* Bit definitions and macros for SCM_CFIER */ 159*4882a593Smuzhiyun #define CFIER_ECFEI (0x01) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* Bit definitions and macros for SCM_CFLOC */ 162*4882a593Smuzhiyun #define CFLOC_LOC (0x80) 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* Bit definitions and macros for SCM_CFATR */ 165*4882a593Smuzhiyun #define CFATR_WRITE (0x80) 166*4882a593Smuzhiyun #define CFATR_SZ32 (0x20) 167*4882a593Smuzhiyun #define CFATR_SZ16 (0x10) 168*4882a593Smuzhiyun #define CFATR_SZ08 (0x00) 169*4882a593Smuzhiyun #define CFATR_CACHE (0x08) 170*4882a593Smuzhiyun #define CFATR_MODE (0x02) 171*4882a593Smuzhiyun #define CFATR_TYPE (0x01) 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun /********************************************************************* 174*4882a593Smuzhiyun * Reset Controller Module (RCM) 175*4882a593Smuzhiyun *********************************************************************/ 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* Bit definitions and macros for RCR */ 178*4882a593Smuzhiyun #define RCM_RCR_FRCRSTOUT (0x40) 179*4882a593Smuzhiyun #define RCM_RCR_SOFTRST (0x80) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* Bit definitions and macros for RSR */ 182*4882a593Smuzhiyun #define RCM_RSR_LOL (0x01) 183*4882a593Smuzhiyun #define RCM_RSR_WDR_CORE (0x02) 184*4882a593Smuzhiyun #define RCM_RSR_EXT (0x04) 185*4882a593Smuzhiyun #define RCM_RSR_POR (0x08) 186*4882a593Smuzhiyun #define RCM_RSR_SOFT (0x20) 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /********************************************************************* 189*4882a593Smuzhiyun * Interrupt Controller (INTC) 190*4882a593Smuzhiyun *********************************************************************/ 191*4882a593Smuzhiyun #define INTC0_EPORT INTC_IPRL_INT1 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define INT0_LO_RSVD0 (0) 194*4882a593Smuzhiyun #define INT0_LO_EPORT1 (1) 195*4882a593Smuzhiyun #define INT0_LO_EPORT2 (2) 196*4882a593Smuzhiyun #define INT0_LO_EPORT3 (3) 197*4882a593Smuzhiyun #define INT0_LO_EPORT4 (4) 198*4882a593Smuzhiyun #define INT0_LO_EPORT5 (5) 199*4882a593Smuzhiyun #define INT0_LO_EPORT6 (6) 200*4882a593Smuzhiyun #define INT0_LO_EPORT7 (7) 201*4882a593Smuzhiyun #define INT0_LO_EDMA_00 (8) 202*4882a593Smuzhiyun #define INT0_LO_EDMA_01 (9) 203*4882a593Smuzhiyun #define INT0_LO_EDMA_02 (10) 204*4882a593Smuzhiyun #define INT0_LO_EDMA_03 (11) 205*4882a593Smuzhiyun #define INT0_LO_EDMA_04 (12) 206*4882a593Smuzhiyun #define INT0_LO_EDMA_05 (13) 207*4882a593Smuzhiyun #define INT0_LO_EDMA_06 (14) 208*4882a593Smuzhiyun #define INT0_LO_EDMA_07 (15) 209*4882a593Smuzhiyun #define INT0_LO_EDMA_08 (16) 210*4882a593Smuzhiyun #define INT0_LO_EDMA_09 (17) 211*4882a593Smuzhiyun #define INT0_LO_EDMA_10 (18) 212*4882a593Smuzhiyun #define INT0_LO_EDMA_11 (19) 213*4882a593Smuzhiyun #define INT0_LO_EDMA_12 (20) 214*4882a593Smuzhiyun #define INT0_LO_EDMA_13 (21) 215*4882a593Smuzhiyun #define INT0_LO_EDMA_14 (22) 216*4882a593Smuzhiyun #define INT0_LO_EDMA_15 (23) 217*4882a593Smuzhiyun #define INT0_LO_EDMA_ERR (24) 218*4882a593Smuzhiyun #define INT0_LO_SCM (25) 219*4882a593Smuzhiyun #define INT0_LO_UART0 (26) 220*4882a593Smuzhiyun #define INT0_LO_UART1 (27) 221*4882a593Smuzhiyun #define INT0_LO_UART2 (28) 222*4882a593Smuzhiyun #define INT0_LO_RSVD1 (29) 223*4882a593Smuzhiyun #define INT0_LO_I2C (30) 224*4882a593Smuzhiyun #define INT0_LO_QSPI (31) 225*4882a593Smuzhiyun #define INT0_HI_DTMR0 (32) 226*4882a593Smuzhiyun #define INT0_HI_DTMR1 (33) 227*4882a593Smuzhiyun #define INT0_HI_DTMR2 (34) 228*4882a593Smuzhiyun #define INT0_HI_DTMR3 (35) 229*4882a593Smuzhiyun #define INT0_HI_FEC_TXF (36) 230*4882a593Smuzhiyun #define INT0_HI_FEC_TXB (37) 231*4882a593Smuzhiyun #define INT0_HI_FEC_UN (38) 232*4882a593Smuzhiyun #define INT0_HI_FEC_RL (39) 233*4882a593Smuzhiyun #define INT0_HI_FEC_RXF (40) 234*4882a593Smuzhiyun #define INT0_HI_FEC_RXB (41) 235*4882a593Smuzhiyun #define INT0_HI_FEC_MII (42) 236*4882a593Smuzhiyun #define INT0_HI_FEC_LC (43) 237*4882a593Smuzhiyun #define INT0_HI_FEC_HBERR (44) 238*4882a593Smuzhiyun #define INT0_HI_FEC_GRA (45) 239*4882a593Smuzhiyun #define INT0_HI_FEC_EBERR (46) 240*4882a593Smuzhiyun #define INT0_HI_FEC_BABT (47) 241*4882a593Smuzhiyun #define INT0_HI_FEC_BABR (48) 242*4882a593Smuzhiyun /* 49 - 61 Reserved */ 243*4882a593Smuzhiyun #define INT0_HI_SCM (62) 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /********************************************************************* 246*4882a593Smuzhiyun * Watchdog Timer Modules (WTM) 247*4882a593Smuzhiyun *********************************************************************/ 248*4882a593Smuzhiyun /* Bit definitions and macros for WTM_WCR */ 249*4882a593Smuzhiyun #define WTM_WCR_WAIT (0x0008) 250*4882a593Smuzhiyun #define WTM_WCR_DOZE (0x0004) 251*4882a593Smuzhiyun #define WTM_WCR_HALTED (0x0002) 252*4882a593Smuzhiyun #define WTM_WCR_EN (0x0001) 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun /********************************************************************* 255*4882a593Smuzhiyun * Chip Configuration Module (CCM) 256*4882a593Smuzhiyun *********************************************************************/ 257*4882a593Smuzhiyun /* Bit definitions and macros for CCM_CCR */ 258*4882a593Smuzhiyun #define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) 259*4882a593Smuzhiyun #define CCM_CCR_LIMP (0x0041) 260*4882a593Smuzhiyun #define CCM_CCR_LOAD (0x0021) 261*4882a593Smuzhiyun #define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) 262*4882a593Smuzhiyun #define CCM_CCR_OSC_MODE (0x0005) 263*4882a593Smuzhiyun #define CCM_CCR_PLL_MODE (0x0003) 264*4882a593Smuzhiyun #define CCM_CCR_RESERVED (0x0001) 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /* Bit definitions and macros for CCM_RCON */ 267*4882a593Smuzhiyun #define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) 268*4882a593Smuzhiyun #define CCM_RCON_LIMP (0x0041) 269*4882a593Smuzhiyun #define CCM_RCON_LOAD (0x0021) 270*4882a593Smuzhiyun #define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) 271*4882a593Smuzhiyun #define CCM_RCON_OSC_MODE (0x0005) 272*4882a593Smuzhiyun #define CCM_RCON_PLL_MODE (0x0003) 273*4882a593Smuzhiyun #define CCM_RCON_RESERVED (0x0001) 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun /* Bit definitions and macros for CCM_CIR */ 276*4882a593Smuzhiyun #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) 277*4882a593Smuzhiyun #define CCM_CIR_PRN(x) ((x)&0x003F) 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun /* Bit definitions and macros for CCM_MISCCR */ 280*4882a593Smuzhiyun #define CCM_MISCCR_PLL_LOCK (0x2000) 281*4882a593Smuzhiyun #define CCM_MISCCR_LIMP (0x1000) 282*4882a593Smuzhiyun #define CCM_MISCCR_LCD_CHEN (0x0100) 283*4882a593Smuzhiyun #define CCM_MISCCR_SSI_PUE (0x0080) 284*4882a593Smuzhiyun #define CCM_MISCCR_SSI_PUS (0x0040) 285*4882a593Smuzhiyun #define CCM_MISCCR_TIM_DMA (0x0020) 286*4882a593Smuzhiyun #define CCM_MISCCR_SSI_SRC (0x0010) 287*4882a593Smuzhiyun #define CCM_MISCCR_USBDIV (0x0002) 288*4882a593Smuzhiyun #define CCM_MISCCR_USBSRC (0x0001) 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun /* Bit definitions and macros for CCM_CDR */ 291*4882a593Smuzhiyun #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) 292*4882a593Smuzhiyun #define CCM_CDR_SSIDIV(x) ((x)&0x000F) 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /* Bit definitions and macros for CCM_UHCSR */ 295*4882a593Smuzhiyun #define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) 296*4882a593Smuzhiyun #define CCM_UHCSR_WKUP (0x0004) 297*4882a593Smuzhiyun #define CCM_UHCSR_UHMIE (0x0002) 298*4882a593Smuzhiyun #define CCM_UHCSR_XPDE (0x0001) 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun /* Bit definitions and macros for CCM_UOCSR */ 301*4882a593Smuzhiyun #define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) 302*4882a593Smuzhiyun #define CCM_UOCSR_DPPD (0x2000) 303*4882a593Smuzhiyun #define CCM_UOCSR_DMPD (0x1000) 304*4882a593Smuzhiyun #define CCM_UOCSR_DRV_VBUS (0x0800) 305*4882a593Smuzhiyun #define CCM_UOCSR_CRG_VBUS (0x0400) 306*4882a593Smuzhiyun #define CCM_UOCSR_DCR_VBUS (0x0200) 307*4882a593Smuzhiyun #define CCM_UOCSR_DPPU (0x0100) 308*4882a593Smuzhiyun #define CCM_UOCSR_AVLD (0x0080) 309*4882a593Smuzhiyun #define CCM_UOCSR_BVLD (0x0040) 310*4882a593Smuzhiyun #define CCM_UOCSR_VVLD (0x0020) 311*4882a593Smuzhiyun #define CCM_UOCSR_SEND (0x0010) 312*4882a593Smuzhiyun #define CCM_UOCSR_PWRFLT (0x0008) 313*4882a593Smuzhiyun #define CCM_UOCSR_WKUP (0x0004) 314*4882a593Smuzhiyun #define CCM_UOCSR_UOMIE (0x0002) 315*4882a593Smuzhiyun #define CCM_UOCSR_XPDE (0x0001) 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun /* not done yet */ 318*4882a593Smuzhiyun /********************************************************************* 319*4882a593Smuzhiyun * General Purpose I/O (GPIO) 320*4882a593Smuzhiyun *********************************************************************/ 321*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_FECH_L */ 322*4882a593Smuzhiyun #define GPIO_PODR_FECH_L7 (0x80) 323*4882a593Smuzhiyun #define GPIO_PODR_FECH_L6 (0x40) 324*4882a593Smuzhiyun #define GPIO_PODR_FECH_L5 (0x20) 325*4882a593Smuzhiyun #define GPIO_PODR_FECH_L4 (0x10) 326*4882a593Smuzhiyun #define GPIO_PODR_FECH_L3 (0x08) 327*4882a593Smuzhiyun #define GPIO_PODR_FECH_L2 (0x04) 328*4882a593Smuzhiyun #define GPIO_PODR_FECH_L1 (0x02) 329*4882a593Smuzhiyun #define GPIO_PODR_FECH_L0 (0x01) 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_SSI */ 332*4882a593Smuzhiyun #define GPIO_PODR_SSI_4 (0x10) 333*4882a593Smuzhiyun #define GPIO_PODR_SSI_3 (0x08) 334*4882a593Smuzhiyun #define GPIO_PODR_SSI_2 (0x04) 335*4882a593Smuzhiyun #define GPIO_PODR_SSI_1 (0x02) 336*4882a593Smuzhiyun #define GPIO_PODR_SSI_0 (0x01) 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_BUSCTL */ 339*4882a593Smuzhiyun #define GPIO_PODR_BUSCTL_3 (0x08) 340*4882a593Smuzhiyun #define GPIO_PODR_BUSCTL_2 (0x04) 341*4882a593Smuzhiyun #define GPIO_PODR_BUSCTL_1 (0x02) 342*4882a593Smuzhiyun #define GPIO_PODR_BUSCTL_0 (0x01) 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_BE */ 345*4882a593Smuzhiyun #define GPIO_PODR_BE_3 (0x08) 346*4882a593Smuzhiyun #define GPIO_PODR_BE_2 (0x04) 347*4882a593Smuzhiyun #define GPIO_PODR_BE_1 (0x02) 348*4882a593Smuzhiyun #define GPIO_PODR_BE_0 (0x01) 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_CS */ 351*4882a593Smuzhiyun #define GPIO_PODR_CS_5 (0x20) 352*4882a593Smuzhiyun #define GPIO_PODR_CS_4 (0x10) 353*4882a593Smuzhiyun #define GPIO_PODR_CS_3 (0x08) 354*4882a593Smuzhiyun #define GPIO_PODR_CS_2 (0x04) 355*4882a593Smuzhiyun #define GPIO_PODR_CS_1 (0x02) 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_PWM */ 358*4882a593Smuzhiyun #define GPIO_PODR_PWM_5 (0x20) 359*4882a593Smuzhiyun #define GPIO_PODR_PWM_4 (0x10) 360*4882a593Smuzhiyun #define GPIO_PODR_PWM_3 (0x08) 361*4882a593Smuzhiyun #define GPIO_PODR_PWM_2 (0x04) 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_FECI2C */ 364*4882a593Smuzhiyun #define GPIO_PODR_FECI2C_3 (0x08) 365*4882a593Smuzhiyun #define GPIO_PODR_FECI2C_2 (0x04) 366*4882a593Smuzhiyun #define GPIO_PODR_FECI2C_1 (0x02) 367*4882a593Smuzhiyun #define GPIO_PODR_FECI2C_0 (0x01) 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_UART */ 370*4882a593Smuzhiyun #define GPIO_PODR_UART_7 (0x80) 371*4882a593Smuzhiyun #define GPIO_PODR_UART_6 (0x40) 372*4882a593Smuzhiyun #define GPIO_PODR_UART_5 (0x20) 373*4882a593Smuzhiyun #define GPIO_PODR_UART_4 (0x10) 374*4882a593Smuzhiyun #define GPIO_PODR_UART_3 (0x08) 375*4882a593Smuzhiyun #define GPIO_PODR_UART_2 (0x04) 376*4882a593Smuzhiyun #define GPIO_PODR_UART_1 (0x02) 377*4882a593Smuzhiyun #define GPIO_PODR_UART_0 (0x01) 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_QSPI */ 380*4882a593Smuzhiyun #define GPIO_PODR_QSPI_5 (0x20) 381*4882a593Smuzhiyun #define GPIO_PODR_QSPI_4 (0x10) 382*4882a593Smuzhiyun #define GPIO_PODR_QSPI_3 (0x08) 383*4882a593Smuzhiyun #define GPIO_PODR_QSPI_2 (0x04) 384*4882a593Smuzhiyun #define GPIO_PODR_QSPI_1 (0x02) 385*4882a593Smuzhiyun #define GPIO_PODR_QSPI_0 (0x01) 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_TIMER */ 388*4882a593Smuzhiyun #define GPIO_PODR_TIMER_3 (0x08) 389*4882a593Smuzhiyun #define GPIO_PODR_TIMER_2 (0x04) 390*4882a593Smuzhiyun #define GPIO_PODR_TIMER_1 (0x02) 391*4882a593Smuzhiyun #define GPIO_PODR_TIMER_0 (0x01) 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_LCDDATAH */ 394*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAH_1 (0x02) 395*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAH_0 (0x01) 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_LCDDATAM */ 398*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAM_7 (0x80) 399*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAM_6 (0x40) 400*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAM_5 (0x20) 401*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAM_4 (0x10) 402*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAM_3 (0x08) 403*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAM_2 (0x04) 404*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAM_1 (0x02) 405*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAM_0 (0x01) 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_LCDDATAL */ 408*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAL_7 (0x80) 409*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAL_6 (0x40) 410*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAL_5 (0x20) 411*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAL_4 (0x10) 412*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAL_3 (0x08) 413*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAL_2 (0x04) 414*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAL_1 (0x02) 415*4882a593Smuzhiyun #define GPIO_PODR_LCDDATAL_0 (0x01) 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_LCDCTLH */ 418*4882a593Smuzhiyun #define GPIO_PODR_LCDCTLH_0 (0x01) 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR_LCDCTLL */ 421*4882a593Smuzhiyun #define GPIO_PODR_LCDCTLL_7 (0x80) 422*4882a593Smuzhiyun #define GPIO_PODR_LCDCTLL_6 (0x40) 423*4882a593Smuzhiyun #define GPIO_PODR_LCDCTLL_5 (0x20) 424*4882a593Smuzhiyun #define GPIO_PODR_LCDCTLL_4 (0x10) 425*4882a593Smuzhiyun #define GPIO_PODR_LCDCTLL_3 (0x08) 426*4882a593Smuzhiyun #define GPIO_PODR_LCDCTLL_2 (0x04) 427*4882a593Smuzhiyun #define GPIO_PODR_LCDCTLL_1 (0x02) 428*4882a593Smuzhiyun #define GPIO_PODR_LCDCTLL_0 (0x01) 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_FECH */ 431*4882a593Smuzhiyun #define GPIO_PDDR_FECH_L7 (0x80) 432*4882a593Smuzhiyun #define GPIO_PDDR_FECH_L6 (0x40) 433*4882a593Smuzhiyun #define GPIO_PDDR_FECH_L5 (0x20) 434*4882a593Smuzhiyun #define GPIO_PDDR_FECH_L4 (0x10) 435*4882a593Smuzhiyun #define GPIO_PDDR_FECH_L3 (0x08) 436*4882a593Smuzhiyun #define GPIO_PDDR_FECH_L2 (0x04) 437*4882a593Smuzhiyun #define GPIO_PDDR_FECH_L1 (0x02) 438*4882a593Smuzhiyun #define GPIO_PDDR_FECH_L0 (0x01) 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_SSI */ 441*4882a593Smuzhiyun #define GPIO_PDDR_SSI_4 (0x10) 442*4882a593Smuzhiyun #define GPIO_PDDR_SSI_3 (0x08) 443*4882a593Smuzhiyun #define GPIO_PDDR_SSI_2 (0x04) 444*4882a593Smuzhiyun #define GPIO_PDDR_SSI_1 (0x02) 445*4882a593Smuzhiyun #define GPIO_PDDR_SSI_0 (0x01) 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_BUSCTL */ 448*4882a593Smuzhiyun #define GPIO_PDDR_BUSCTL_3 (0x08) 449*4882a593Smuzhiyun #define GPIO_PDDR_BUSCTL_2 (0x04) 450*4882a593Smuzhiyun #define GPIO_PDDR_BUSCTL_1 (0x02) 451*4882a593Smuzhiyun #define GPIO_PDDR_BUSCTL_0 (0x01) 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_BE */ 454*4882a593Smuzhiyun #define GPIO_PDDR_BE_3 (0x08) 455*4882a593Smuzhiyun #define GPIO_PDDR_BE_2 (0x04) 456*4882a593Smuzhiyun #define GPIO_PDDR_BE_1 (0x02) 457*4882a593Smuzhiyun #define GPIO_PDDR_BE_0 (0x01) 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_CS */ 460*4882a593Smuzhiyun #define GPIO_PDDR_CS_1 (0x02) 461*4882a593Smuzhiyun #define GPIO_PDDR_CS_2 (0x04) 462*4882a593Smuzhiyun #define GPIO_PDDR_CS_3 (0x08) 463*4882a593Smuzhiyun #define GPIO_PDDR_CS_4 (0x10) 464*4882a593Smuzhiyun #define GPIO_PDDR_CS_5 (0x20) 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_PWM */ 467*4882a593Smuzhiyun #define GPIO_PDDR_PWM_2 (0x04) 468*4882a593Smuzhiyun #define GPIO_PDDR_PWM_3 (0x08) 469*4882a593Smuzhiyun #define GPIO_PDDR_PWM_4 (0x10) 470*4882a593Smuzhiyun #define GPIO_PDDR_PWM_5 (0x20) 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_FECI2C */ 473*4882a593Smuzhiyun #define GPIO_PDDR_FECI2C_0 (0x01) 474*4882a593Smuzhiyun #define GPIO_PDDR_FECI2C_1 (0x02) 475*4882a593Smuzhiyun #define GPIO_PDDR_FECI2C_2 (0x04) 476*4882a593Smuzhiyun #define GPIO_PDDR_FECI2C_3 (0x08) 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_UART */ 479*4882a593Smuzhiyun #define GPIO_PDDR_UART_0 (0x01) 480*4882a593Smuzhiyun #define GPIO_PDDR_UART_1 (0x02) 481*4882a593Smuzhiyun #define GPIO_PDDR_UART_2 (0x04) 482*4882a593Smuzhiyun #define GPIO_PDDR_UART_3 (0x08) 483*4882a593Smuzhiyun #define GPIO_PDDR_UART_4 (0x10) 484*4882a593Smuzhiyun #define GPIO_PDDR_UART_5 (0x20) 485*4882a593Smuzhiyun #define GPIO_PDDR_UART_6 (0x40) 486*4882a593Smuzhiyun #define GPIO_PDDR_UART_7 (0x80) 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_QSPI */ 489*4882a593Smuzhiyun #define GPIO_PDDR_QSPI_0 (0x01) 490*4882a593Smuzhiyun #define GPIO_PDDR_QSPI_1 (0x02) 491*4882a593Smuzhiyun #define GPIO_PDDR_QSPI_2 (0x04) 492*4882a593Smuzhiyun #define GPIO_PDDR_QSPI_3 (0x08) 493*4882a593Smuzhiyun #define GPIO_PDDR_QSPI_4 (0x10) 494*4882a593Smuzhiyun #define GPIO_PDDR_QSPI_5 (0x20) 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_TIMER */ 497*4882a593Smuzhiyun #define GPIO_PDDR_TIMER_0 (0x01) 498*4882a593Smuzhiyun #define GPIO_PDDR_TIMER_1 (0x02) 499*4882a593Smuzhiyun #define GPIO_PDDR_TIMER_2 (0x04) 500*4882a593Smuzhiyun #define GPIO_PDDR_TIMER_3 (0x08) 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_LCDDATAH */ 503*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAH_0 (0x01) 504*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAH_1 (0x02) 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_LCDDATAM */ 507*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAM_0 (0x01) 508*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAM_1 (0x02) 509*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAM_2 (0x04) 510*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAM_3 (0x08) 511*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAM_4 (0x10) 512*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAM_5 (0x20) 513*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAM_6 (0x40) 514*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAM_7 (0x80) 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_LCDDATAL */ 517*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAL_0 (0x01) 518*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAL_1 (0x02) 519*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAL_2 (0x04) 520*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAL_3 (0x08) 521*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAL_4 (0x10) 522*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAL_5 (0x20) 523*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAL_6 (0x40) 524*4882a593Smuzhiyun #define GPIO_PDDR_LCDDATAL_7 (0x80) 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_LCDCTLH */ 527*4882a593Smuzhiyun #define GPIO_PDDR_LCDCTLH_0 (0x01) 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR_LCDCTLL */ 530*4882a593Smuzhiyun #define GPIO_PDDR_LCDCTLL_0 (0x01) 531*4882a593Smuzhiyun #define GPIO_PDDR_LCDCTLL_1 (0x02) 532*4882a593Smuzhiyun #define GPIO_PDDR_LCDCTLL_2 (0x04) 533*4882a593Smuzhiyun #define GPIO_PDDR_LCDCTLL_3 (0x08) 534*4882a593Smuzhiyun #define GPIO_PDDR_LCDCTLL_4 (0x10) 535*4882a593Smuzhiyun #define GPIO_PDDR_LCDCTLL_5 (0x20) 536*4882a593Smuzhiyun #define GPIO_PDDR_LCDCTLL_6 (0x40) 537*4882a593Smuzhiyun #define GPIO_PDDR_LCDCTLL_7 (0x80) 538*4882a593Smuzhiyun 539*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_FECH */ 540*4882a593Smuzhiyun #define GPIO_PPDSDR_FECH_L0 (0x01) 541*4882a593Smuzhiyun #define GPIO_PPDSDR_FECH_L1 (0x02) 542*4882a593Smuzhiyun #define GPIO_PPDSDR_FECH_L2 (0x04) 543*4882a593Smuzhiyun #define GPIO_PPDSDR_FECH_L3 (0x08) 544*4882a593Smuzhiyun #define GPIO_PPDSDR_FECH_L4 (0x10) 545*4882a593Smuzhiyun #define GPIO_PPDSDR_FECH_L5 (0x20) 546*4882a593Smuzhiyun #define GPIO_PPDSDR_FECH_L6 (0x40) 547*4882a593Smuzhiyun #define GPIO_PPDSDR_FECH_L7 (0x80) 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_SSI */ 550*4882a593Smuzhiyun #define GPIO_PPDSDR_SSI_0 (0x01) 551*4882a593Smuzhiyun #define GPIO_PPDSDR_SSI_1 (0x02) 552*4882a593Smuzhiyun #define GPIO_PPDSDR_SSI_2 (0x04) 553*4882a593Smuzhiyun #define GPIO_PPDSDR_SSI_3 (0x08) 554*4882a593Smuzhiyun #define GPIO_PPDSDR_SSI_4 (0x10) 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */ 557*4882a593Smuzhiyun #define GPIO_PPDSDR_BUSCTL_0 (0x01) 558*4882a593Smuzhiyun #define GPIO_PPDSDR_BUSCTL_1 (0x02) 559*4882a593Smuzhiyun #define GPIO_PPDSDR_BUSCTL_2 (0x04) 560*4882a593Smuzhiyun #define GPIO_PPDSDR_BUSCTL_3 (0x08) 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_BE */ 563*4882a593Smuzhiyun #define GPIO_PPDSDR_BE_0 (0x01) 564*4882a593Smuzhiyun #define GPIO_PPDSDR_BE_1 (0x02) 565*4882a593Smuzhiyun #define GPIO_PPDSDR_BE_2 (0x04) 566*4882a593Smuzhiyun #define GPIO_PPDSDR_BE_3 (0x08) 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_CS */ 569*4882a593Smuzhiyun #define GPIO_PPDSDR_CS_1 (0x02) 570*4882a593Smuzhiyun #define GPIO_PPDSDR_CS_2 (0x04) 571*4882a593Smuzhiyun #define GPIO_PPDSDR_CS_3 (0x08) 572*4882a593Smuzhiyun #define GPIO_PPDSDR_CS_4 (0x10) 573*4882a593Smuzhiyun #define GPIO_PPDSDR_CS_5 (0x20) 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_PWM */ 576*4882a593Smuzhiyun #define GPIO_PPDSDR_PWM_2 (0x04) 577*4882a593Smuzhiyun #define GPIO_PPDSDR_PWM_3 (0x08) 578*4882a593Smuzhiyun #define GPIO_PPDSDR_PWM_4 (0x10) 579*4882a593Smuzhiyun #define GPIO_PPDSDR_PWM_5 (0x20) 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_FECI2C */ 582*4882a593Smuzhiyun #define GPIO_PPDSDR_FECI2C_0 (0x01) 583*4882a593Smuzhiyun #define GPIO_PPDSDR_FECI2C_1 (0x02) 584*4882a593Smuzhiyun #define GPIO_PPDSDR_FECI2C_2 (0x04) 585*4882a593Smuzhiyun #define GPIO_PPDSDR_FECI2C_3 (0x08) 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_UART */ 588*4882a593Smuzhiyun #define GPIO_PPDSDR_UART_0 (0x01) 589*4882a593Smuzhiyun #define GPIO_PPDSDR_UART_1 (0x02) 590*4882a593Smuzhiyun #define GPIO_PPDSDR_UART_2 (0x04) 591*4882a593Smuzhiyun #define GPIO_PPDSDR_UART_3 (0x08) 592*4882a593Smuzhiyun #define GPIO_PPDSDR_UART_4 (0x10) 593*4882a593Smuzhiyun #define GPIO_PPDSDR_UART_5 (0x20) 594*4882a593Smuzhiyun #define GPIO_PPDSDR_UART_6 (0x40) 595*4882a593Smuzhiyun #define GPIO_PPDSDR_UART_7 (0x80) 596*4882a593Smuzhiyun 597*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_QSPI */ 598*4882a593Smuzhiyun #define GPIO_PPDSDR_QSPI_0 (0x01) 599*4882a593Smuzhiyun #define GPIO_PPDSDR_QSPI_1 (0x02) 600*4882a593Smuzhiyun #define GPIO_PPDSDR_QSPI_2 (0x04) 601*4882a593Smuzhiyun #define GPIO_PPDSDR_QSPI_3 (0x08) 602*4882a593Smuzhiyun #define GPIO_PPDSDR_QSPI_4 (0x10) 603*4882a593Smuzhiyun #define GPIO_PPDSDR_QSPI_5 (0x20) 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_TIMER */ 606*4882a593Smuzhiyun #define GPIO_PPDSDR_TIMER_0 (0x01) 607*4882a593Smuzhiyun #define GPIO_PPDSDR_TIMER_1 (0x02) 608*4882a593Smuzhiyun #define GPIO_PPDSDR_TIMER_2 (0x04) 609*4882a593Smuzhiyun #define GPIO_PPDSDR_TIMER_3 (0x08) 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */ 612*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAH_0 (0x01) 613*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAH_1 (0x02) 614*4882a593Smuzhiyun 615*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */ 616*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAM_0 (0x01) 617*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAM_1 (0x02) 618*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAM_2 (0x04) 619*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAM_3 (0x08) 620*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAM_4 (0x10) 621*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAM_5 (0x20) 622*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAM_6 (0x40) 623*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAM_7 (0x80) 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */ 626*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAL_0 (0x01) 627*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAL_1 (0x02) 628*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAL_2 (0x04) 629*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAL_3 (0x08) 630*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAL_4 (0x10) 631*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAL_5 (0x20) 632*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAL_6 (0x40) 633*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDDATAL_7 (0x80) 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */ 636*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDCTLH_0 (0x01) 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */ 639*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDCTLL_0 (0x01) 640*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDCTLL_1 (0x02) 641*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDCTLL_2 (0x04) 642*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDCTLL_3 (0x08) 643*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDCTLL_4 (0x10) 644*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDCTLL_5 (0x20) 645*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDCTLL_6 (0x40) 646*4882a593Smuzhiyun #define GPIO_PPDSDR_LCDCTLL_7 (0x80) 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_FECH */ 649*4882a593Smuzhiyun #define GPIO_PCLRR_FECH_L0 (0x01) 650*4882a593Smuzhiyun #define GPIO_PCLRR_FECH_L1 (0x02) 651*4882a593Smuzhiyun #define GPIO_PCLRR_FECH_L2 (0x04) 652*4882a593Smuzhiyun #define GPIO_PCLRR_FECH_L3 (0x08) 653*4882a593Smuzhiyun #define GPIO_PCLRR_FECH_L4 (0x10) 654*4882a593Smuzhiyun #define GPIO_PCLRR_FECH_L5 (0x20) 655*4882a593Smuzhiyun #define GPIO_PCLRR_FECH_L6 (0x40) 656*4882a593Smuzhiyun #define GPIO_PCLRR_FECH_L7 (0x80) 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_SSI */ 659*4882a593Smuzhiyun #define GPIO_PCLRR_SSI_0 (0x01) 660*4882a593Smuzhiyun #define GPIO_PCLRR_SSI_1 (0x02) 661*4882a593Smuzhiyun #define GPIO_PCLRR_SSI_2 (0x04) 662*4882a593Smuzhiyun #define GPIO_PCLRR_SSI_3 (0x08) 663*4882a593Smuzhiyun #define GPIO_PCLRR_SSI_4 (0x10) 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_BUSCTL */ 666*4882a593Smuzhiyun #define GPIO_PCLRR_BUSCTL_L0 (0x01) 667*4882a593Smuzhiyun #define GPIO_PCLRR_BUSCTL_L1 (0x02) 668*4882a593Smuzhiyun #define GPIO_PCLRR_BUSCTL_L2 (0x04) 669*4882a593Smuzhiyun #define GPIO_PCLRR_BUSCTL_L3 (0x08) 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_BE */ 672*4882a593Smuzhiyun #define GPIO_PCLRR_BE_0 (0x01) 673*4882a593Smuzhiyun #define GPIO_PCLRR_BE_1 (0x02) 674*4882a593Smuzhiyun #define GPIO_PCLRR_BE_2 (0x04) 675*4882a593Smuzhiyun #define GPIO_PCLRR_BE_3 (0x08) 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_CS */ 678*4882a593Smuzhiyun #define GPIO_PCLRR_CS_1 (0x02) 679*4882a593Smuzhiyun #define GPIO_PCLRR_CS_2 (0x04) 680*4882a593Smuzhiyun #define GPIO_PCLRR_CS_3 (0x08) 681*4882a593Smuzhiyun #define GPIO_PCLRR_CS_4 (0x10) 682*4882a593Smuzhiyun #define GPIO_PCLRR_CS_5 (0x20) 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_PWM */ 685*4882a593Smuzhiyun #define GPIO_PCLRR_PWM_2 (0x04) 686*4882a593Smuzhiyun #define GPIO_PCLRR_PWM_3 (0x08) 687*4882a593Smuzhiyun #define GPIO_PCLRR_PWM_4 (0x10) 688*4882a593Smuzhiyun #define GPIO_PCLRR_PWM_5 (0x20) 689*4882a593Smuzhiyun 690*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_FECI2C */ 691*4882a593Smuzhiyun #define GPIO_PCLRR_FECI2C_0 (0x01) 692*4882a593Smuzhiyun #define GPIO_PCLRR_FECI2C_1 (0x02) 693*4882a593Smuzhiyun #define GPIO_PCLRR_FECI2C_2 (0x04) 694*4882a593Smuzhiyun #define GPIO_PCLRR_FECI2C_3 (0x08) 695*4882a593Smuzhiyun 696*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_UART */ 697*4882a593Smuzhiyun #define GPIO_PCLRR_UART0 (0x01) 698*4882a593Smuzhiyun #define GPIO_PCLRR_UART1 (0x02) 699*4882a593Smuzhiyun #define GPIO_PCLRR_UART2 (0x04) 700*4882a593Smuzhiyun #define GPIO_PCLRR_UART3 (0x08) 701*4882a593Smuzhiyun #define GPIO_PCLRR_UART4 (0x10) 702*4882a593Smuzhiyun #define GPIO_PCLRR_UART5 (0x20) 703*4882a593Smuzhiyun #define GPIO_PCLRR_UART6 (0x40) 704*4882a593Smuzhiyun #define GPIO_PCLRR_UART7 (0x80) 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_QSPI */ 707*4882a593Smuzhiyun #define GPIO_PCLRR_QSPI0 (0x01) 708*4882a593Smuzhiyun #define GPIO_PCLRR_QSPI1 (0x02) 709*4882a593Smuzhiyun #define GPIO_PCLRR_QSPI2 (0x04) 710*4882a593Smuzhiyun #define GPIO_PCLRR_QSPI3 (0x08) 711*4882a593Smuzhiyun #define GPIO_PCLRR_QSPI4 (0x10) 712*4882a593Smuzhiyun #define GPIO_PCLRR_QSPI5 (0x20) 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_TIMER */ 715*4882a593Smuzhiyun #define GPIO_PCLRR_TIMER0 (0x01) 716*4882a593Smuzhiyun #define GPIO_PCLRR_TIMER1 (0x02) 717*4882a593Smuzhiyun #define GPIO_PCLRR_TIMER2 (0x04) 718*4882a593Smuzhiyun #define GPIO_PCLRR_TIMER3 (0x08) 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */ 721*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAH0 (0x01) 722*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAH1 (0x02) 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */ 725*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAM0 (0x01) 726*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAM1 (0x02) 727*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAM2 (0x04) 728*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAM3 (0x08) 729*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAM4 (0x10) 730*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAM5 (0x20) 731*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAM6 (0x40) 732*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAM7 (0x80) 733*4882a593Smuzhiyun 734*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */ 735*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAL0 (0x01) 736*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAL1 (0x02) 737*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAL2 (0x04) 738*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAL3 (0x08) 739*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAL4 (0x10) 740*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAL5 (0x20) 741*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAL6 (0x40) 742*4882a593Smuzhiyun #define GPIO_PCLRR_LCDDATAL7 (0x80) 743*4882a593Smuzhiyun 744*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */ 745*4882a593Smuzhiyun #define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) 746*4882a593Smuzhiyun 747*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */ 748*4882a593Smuzhiyun #define GPIO_PCLRR_LCDCTLL0 (0x01) 749*4882a593Smuzhiyun #define GPIO_PCLRR_LCDCTLL1 (0x02) 750*4882a593Smuzhiyun #define GPIO_PCLRR_LCDCTLL2 (0x04) 751*4882a593Smuzhiyun #define GPIO_PCLRR_LCDCTLL3 (0x08) 752*4882a593Smuzhiyun #define GPIO_PCLRR_LCDCTLL4 (0x10) 753*4882a593Smuzhiyun #define GPIO_PCLRR_LCDCTLL5 (0x20) 754*4882a593Smuzhiyun #define GPIO_PCLRR_LCDCTLL6 (0x40) 755*4882a593Smuzhiyun #define GPIO_PCLRR_LCDCTLL7 (0x80) 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_FEC */ 758*4882a593Smuzhiyun #ifdef CONFIG_M5329 759*4882a593Smuzhiyun #define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0) 760*4882a593Smuzhiyun #define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2) 761*4882a593Smuzhiyun #define GPIO_PAR_FEC_7W_GPIO (0x00) 762*4882a593Smuzhiyun #define GPIO_PAR_FEC_7W_URTS1 (0x04) 763*4882a593Smuzhiyun #define GPIO_PAR_FEC_7W_FEC (0x0C) 764*4882a593Smuzhiyun #define GPIO_PAR_FEC_MII_GPIO (0x00) 765*4882a593Smuzhiyun #define GPIO_PAR_FEC_MII_UART (0x01) 766*4882a593Smuzhiyun #define GPIO_PAR_FEC_MII_FEC (0x03) 767*4882a593Smuzhiyun #else 768*4882a593Smuzhiyun #define GPIO_PAR_FEC_7W_FEC (0x08) 769*4882a593Smuzhiyun #define GPIO_PAR_FEC_MII_FEC (0x02) 770*4882a593Smuzhiyun #endif 771*4882a593Smuzhiyun 772*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_PWM */ 773*4882a593Smuzhiyun #define GPIO_PAR_PWM1(x) (((x)&0x03)<<0) 774*4882a593Smuzhiyun #define GPIO_PAR_PWM3(x) (((x)&0x03)<<2) 775*4882a593Smuzhiyun #define GPIO_PAR_PWM5 (0x10) 776*4882a593Smuzhiyun #define GPIO_PAR_PWM7 (0x20) 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_BUSCTL */ 779*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3) 780*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_RWB (0x20) 781*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TA (0x40) 782*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_OE (0x80) 783*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_OE_GPIO (0x00) 784*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_OE_OE (0x80) 785*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TA_GPIO (0x00) 786*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TA_TA (0x40) 787*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_RWB_GPIO (0x00) 788*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_RWB_RWB (0x20) 789*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TS_GPIO (0x00) 790*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TS_DACK0 (0x10) 791*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TS_TS (0x18) 792*4882a593Smuzhiyun 793*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_FECI2C */ 794*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0) 795*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) 796*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4) 797*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6) 798*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC_GPIO (0x00) 799*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40) 800*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC_SCL (0x80) 801*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC_EMDC (0xC0) 802*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO_GPIO (0x00) 803*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10) 804*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO_SDA (0x20) 805*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30) 806*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_GPIO (0x00) 807*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04) 808*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_SCL (0x0C) 809*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_GPIO (0x00) 810*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_URXD2 (0x02) 811*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_SDA (0x03) 812*4882a593Smuzhiyun 813*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_BE */ 814*4882a593Smuzhiyun #define GPIO_PAR_BE0 (0x01) 815*4882a593Smuzhiyun #define GPIO_PAR_BE1 (0x02) 816*4882a593Smuzhiyun #define GPIO_PAR_BE2 (0x04) 817*4882a593Smuzhiyun #define GPIO_PAR_BE3 (0x08) 818*4882a593Smuzhiyun 819*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_CS */ 820*4882a593Smuzhiyun #define GPIO_PAR_CS1 (0x02) 821*4882a593Smuzhiyun #define GPIO_PAR_CS2 (0x04) 822*4882a593Smuzhiyun #define GPIO_PAR_CS3 (0x08) 823*4882a593Smuzhiyun #define GPIO_PAR_CS4 (0x10) 824*4882a593Smuzhiyun #define GPIO_PAR_CS5 (0x20) 825*4882a593Smuzhiyun #define GPIO_PAR_CS1_GPIO (0x00) 826*4882a593Smuzhiyun #define GPIO_PAR_CS1_SDCS1 (0x01) 827*4882a593Smuzhiyun #define GPIO_PAR_CS1_CS1 (0x03) 828*4882a593Smuzhiyun 829*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_SSI */ 830*4882a593Smuzhiyun #define GPIO_PAR_SSI_MCLK (0x0080) 831*4882a593Smuzhiyun #define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8) 832*4882a593Smuzhiyun #define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10) 833*4882a593Smuzhiyun #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12) 834*4882a593Smuzhiyun #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14) 835*4882a593Smuzhiyun 836*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_UART */ 837*4882a593Smuzhiyun #define GPIO_PAR_UART_TXD0 (0x0001) 838*4882a593Smuzhiyun #define GPIO_PAR_UART_RXD0 (0x0002) 839*4882a593Smuzhiyun #define GPIO_PAR_UART_RTS0 (0x0004) 840*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS0 (0x0008) 841*4882a593Smuzhiyun #define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4) 842*4882a593Smuzhiyun #define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6) 843*4882a593Smuzhiyun #define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8) 844*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10) 845*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS1_GPIO (0x0000) 846*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800) 847*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400) 848*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00) 849*4882a593Smuzhiyun #define GPIO_PAR_UART_RTS1_GPIO (0x0000) 850*4882a593Smuzhiyun #define GPIO_PAR_UART_RTS1_SSI_FS (0x0200) 851*4882a593Smuzhiyun #define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100) 852*4882a593Smuzhiyun #define GPIO_PAR_UART_RTS1_URTS1 (0x0300) 853*4882a593Smuzhiyun #define GPIO_PAR_UART_RXD1_GPIO (0x0000) 854*4882a593Smuzhiyun #define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080) 855*4882a593Smuzhiyun #define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040) 856*4882a593Smuzhiyun #define GPIO_PAR_UART_RXD1_URXD1 (0x00C0) 857*4882a593Smuzhiyun #define GPIO_PAR_UART_TXD1_GPIO (0x0000) 858*4882a593Smuzhiyun #define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020) 859*4882a593Smuzhiyun #define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010) 860*4882a593Smuzhiyun #define GPIO_PAR_UART_TXD1_UTXD1 (0x0030) 861*4882a593Smuzhiyun 862*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_QSPI */ 863*4882a593Smuzhiyun #define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4) 864*4882a593Smuzhiyun #define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6) 865*4882a593Smuzhiyun #define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8) 866*4882a593Smuzhiyun #define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10) 867*4882a593Smuzhiyun #define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12) 868*4882a593Smuzhiyun #define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14) 869*4882a593Smuzhiyun 870*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_TIMER */ 871*4882a593Smuzhiyun #define GPIO_PAR_TIN0(x) (((x)&0x03)<<0) 872*4882a593Smuzhiyun #define GPIO_PAR_TIN1(x) (((x)&0x03)<<2) 873*4882a593Smuzhiyun #define GPIO_PAR_TIN2(x) (((x)&0x03)<<4) 874*4882a593Smuzhiyun #define GPIO_PAR_TIN3(x) (((x)&0x03)<<6) 875*4882a593Smuzhiyun #define GPIO_PAR_TIN3_GPIO (0x00) 876*4882a593Smuzhiyun #define GPIO_PAR_TIN3_TOUT3 (0x80) 877*4882a593Smuzhiyun #define GPIO_PAR_TIN3_URXD2 (0x40) 878*4882a593Smuzhiyun #define GPIO_PAR_TIN3_TIN3 (0xC0) 879*4882a593Smuzhiyun #define GPIO_PAR_TIN2_GPIO (0x00) 880*4882a593Smuzhiyun #define GPIO_PAR_TIN2_TOUT2 (0x20) 881*4882a593Smuzhiyun #define GPIO_PAR_TIN2_UTXD2 (0x10) 882*4882a593Smuzhiyun #define GPIO_PAR_TIN2_TIN2 (0x30) 883*4882a593Smuzhiyun #define GPIO_PAR_TIN1_GPIO (0x00) 884*4882a593Smuzhiyun #define GPIO_PAR_TIN1_TOUT1 (0x08) 885*4882a593Smuzhiyun #define GPIO_PAR_TIN1_DACK1 (0x04) 886*4882a593Smuzhiyun #define GPIO_PAR_TIN1_TIN1 (0x0C) 887*4882a593Smuzhiyun #define GPIO_PAR_TIN0_GPIO (0x00) 888*4882a593Smuzhiyun #define GPIO_PAR_TIN0_TOUT0 (0x02) 889*4882a593Smuzhiyun #define GPIO_PAR_TIN0_DREQ0 (0x01) 890*4882a593Smuzhiyun #define GPIO_PAR_TIN0_TIN0 (0x03) 891*4882a593Smuzhiyun 892*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_LCDDATA */ 893*4882a593Smuzhiyun #define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03) 894*4882a593Smuzhiyun #define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2) 895*4882a593Smuzhiyun #define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4) 896*4882a593Smuzhiyun #define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6) 897*4882a593Smuzhiyun 898*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_LCDCTL */ 899*4882a593Smuzhiyun #define GPIO_PAR_LCDCTL_CLS (0x0001) 900*4882a593Smuzhiyun #define GPIO_PAR_LCDCTL_PS (0x0002) 901*4882a593Smuzhiyun #define GPIO_PAR_LCDCTL_REV (0x0004) 902*4882a593Smuzhiyun #define GPIO_PAR_LCDCTL_SPL_SPR (0x0008) 903*4882a593Smuzhiyun #define GPIO_PAR_LCDCTL_CONTRAST (0x0010) 904*4882a593Smuzhiyun #define GPIO_PAR_LCDCTL_LSCLK (0x0020) 905*4882a593Smuzhiyun #define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040) 906*4882a593Smuzhiyun #define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080) 907*4882a593Smuzhiyun #define GPIO_PAR_LCDCTL_ACD_OE (0x0100) 908*4882a593Smuzhiyun 909*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR_IRQ */ 910*4882a593Smuzhiyun #define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4) 911*4882a593Smuzhiyun #define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6) 912*4882a593Smuzhiyun #define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8) 913*4882a593Smuzhiyun #define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10) 914*4882a593Smuzhiyun #define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12) 915*4882a593Smuzhiyun 916*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_MSCR_FLEXBUS */ 917*4882a593Smuzhiyun #define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03) 918*4882a593Smuzhiyun #define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2) 919*4882a593Smuzhiyun #define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4) 920*4882a593Smuzhiyun 921*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_MSCR_SDRAM */ 922*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03) 923*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) 924*4882a593Smuzhiyun #define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4) 925*4882a593Smuzhiyun 926*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_I2C */ 927*4882a593Smuzhiyun #define GPIO_DSCR_I2C_DSE(x) ((x)&0x03) 928*4882a593Smuzhiyun 929*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_PWM */ 930*4882a593Smuzhiyun #define GPIO_DSCR_PWM_DSE(x) ((x)&0x03) 931*4882a593Smuzhiyun 932*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_FEC */ 933*4882a593Smuzhiyun #define GPIO_DSCR_FEC_DSE(x) ((x)&0x03) 934*4882a593Smuzhiyun 935*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_UART */ 936*4882a593Smuzhiyun #define GPIO_DSCR_UART0_DSE(x) ((x)&0x03) 937*4882a593Smuzhiyun #define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2) 938*4882a593Smuzhiyun 939*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_QSPI */ 940*4882a593Smuzhiyun #define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03) 941*4882a593Smuzhiyun 942*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_TIMER */ 943*4882a593Smuzhiyun #define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03) 944*4882a593Smuzhiyun 945*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_SSI */ 946*4882a593Smuzhiyun #define GPIO_DSCR_SSI_DSE(x) ((x)&0x03) 947*4882a593Smuzhiyun 948*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_LCD */ 949*4882a593Smuzhiyun #define GPIO_DSCR_LCD_DSE(x) ((x)&0x03) 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_DEBUG */ 952*4882a593Smuzhiyun #define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03) 953*4882a593Smuzhiyun 954*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_CLKRST */ 955*4882a593Smuzhiyun #define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03) 956*4882a593Smuzhiyun 957*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR_IRQ */ 958*4882a593Smuzhiyun #define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03) 959*4882a593Smuzhiyun 960*4882a593Smuzhiyun /********************************************************************* 961*4882a593Smuzhiyun * SDRAM Controller (SDRAMC) 962*4882a593Smuzhiyun *********************************************************************/ 963*4882a593Smuzhiyun /* Bit definitions and macros for SDRAMC_SDMR */ 964*4882a593Smuzhiyun #define SDRAMC_SDMR_BNKAD_LEMR (0x40000000) 965*4882a593Smuzhiyun #define SDRAMC_SDMR_BNKAD_LMR (0x00000000) 966*4882a593Smuzhiyun #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) 967*4882a593Smuzhiyun #define SDRAMC_SDMR_CMD (0x00010000) 968*4882a593Smuzhiyun 969*4882a593Smuzhiyun /* Bit definitions and macros for SDRAMC_SDCR */ 970*4882a593Smuzhiyun #define SDRAMC_SDCR_MODE_EN (0x80000000) 971*4882a593Smuzhiyun #define SDRAMC_SDCR_CKE (0x40000000) 972*4882a593Smuzhiyun #define SDRAMC_SDCR_DDR (0x20000000) 973*4882a593Smuzhiyun #define SDRAMC_SDCR_REF (0x10000000) 974*4882a593Smuzhiyun #define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) 975*4882a593Smuzhiyun #define SDRAMC_SDCR_OE_RULE (0x00400000) 976*4882a593Smuzhiyun #define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) 977*4882a593Smuzhiyun #define SDRAMC_SDCR_PS_32 (0x00000000) 978*4882a593Smuzhiyun #define SDRAMC_SDCR_PS_16 (0x00002000) 979*4882a593Smuzhiyun #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) 980*4882a593Smuzhiyun #define SDRAMC_SDCR_IREF (0x00000004) 981*4882a593Smuzhiyun #define SDRAMC_SDCR_IPALL (0x00000002) 982*4882a593Smuzhiyun 983*4882a593Smuzhiyun /* Bit definitions and macros for SDRAMC_SDCFG1 */ 984*4882a593Smuzhiyun #define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) 985*4882a593Smuzhiyun #define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) 986*4882a593Smuzhiyun #define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) 987*4882a593Smuzhiyun #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) 988*4882a593Smuzhiyun #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) 989*4882a593Smuzhiyun #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) 990*4882a593Smuzhiyun #define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) 991*4882a593Smuzhiyun 992*4882a593Smuzhiyun /* Bit definitions and macros for SDRAMC_SDCFG2 */ 993*4882a593Smuzhiyun #define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) 994*4882a593Smuzhiyun #define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) 995*4882a593Smuzhiyun #define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) 996*4882a593Smuzhiyun #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) 997*4882a593Smuzhiyun 998*4882a593Smuzhiyun /* Bit definitions and macros for SDRAMC_SDDS */ 999*4882a593Smuzhiyun #define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) 1000*4882a593Smuzhiyun #define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) 1001*4882a593Smuzhiyun #define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) 1002*4882a593Smuzhiyun #define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) 1003*4882a593Smuzhiyun #define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003) 1004*4882a593Smuzhiyun 1005*4882a593Smuzhiyun /* Bit definitions and macros for SDRAMC_SDCS */ 1006*4882a593Smuzhiyun #define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) 1007*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F) 1008*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) 1009*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) 1010*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) 1011*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) 1012*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) 1013*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) 1014*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) 1015*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) 1016*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) 1017*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) 1018*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) 1019*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) 1020*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) 1021*4882a593Smuzhiyun #define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) 1022*4882a593Smuzhiyun 1023*4882a593Smuzhiyun /********************************************************************* 1024*4882a593Smuzhiyun * Phase Locked Loop (PLL) 1025*4882a593Smuzhiyun *********************************************************************/ 1026*4882a593Smuzhiyun /* Bit definitions and macros for PLL_PODR */ 1027*4882a593Smuzhiyun #define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) 1028*4882a593Smuzhiyun #define PLL_PODR_BUSDIV(x) ((x)&0x0F) 1029*4882a593Smuzhiyun 1030*4882a593Smuzhiyun /* Bit definitions and macros for PLL_PLLCR */ 1031*4882a593Smuzhiyun #define PLL_PLLCR_DITHEN (0x80) 1032*4882a593Smuzhiyun #define PLL_PLLCR_DITHDEV(x) ((x)&0x07) 1033*4882a593Smuzhiyun 1034*4882a593Smuzhiyun #endif /* mcf5329_h */ 1035