1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef mcf5307_h 9*4882a593Smuzhiyun #define mcf5307_h 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Size of internal RAM (RAMBAR) 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define INT_RAM_SIZE 4096 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Bit definitions and macros for SYPCR */ 17*4882a593Smuzhiyun #define SYPCR_SWTAVAL 0x02 18*4882a593Smuzhiyun #define SYPCR_SWTA 0x04 19*4882a593Smuzhiyun #define SYPCR_SWT(x) ((x&0x3)<<3) 20*4882a593Smuzhiyun #define SYPCR_SWP 0x20 21*4882a593Smuzhiyun #define SYPCR_SWRI 0x40 22*4882a593Smuzhiyun #define SYPCR_SWE 0x80 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Bit definitions and macros for CSMR */ 25*4882a593Smuzhiyun #define CSMR_V 0x01 26*4882a593Smuzhiyun #define CSMR_UD 0x02 27*4882a593Smuzhiyun #define CSMR_UC 0x04 28*4882a593Smuzhiyun #define CSMR_SD 0x08 29*4882a593Smuzhiyun #define CSMR_SC 0x10 30*4882a593Smuzhiyun #define CSMR_CI 0x20 31*4882a593Smuzhiyun #define CSMR_AM 0x40 32*4882a593Smuzhiyun #define CSMR_WP 0x100 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Bit definitions and macros for DACR (SDRAM) */ 35*4882a593Smuzhiyun #define DACR_PM_CONTINUOUS 0x04 36*4882a593Smuzhiyun #define DACR_IP_PRECHG_ALL 0x08 37*4882a593Smuzhiyun #define DACR_PORT_SZ_32 0 38*4882a593Smuzhiyun #define DACR_PORT_SZ_8 (1<<4) 39*4882a593Smuzhiyun #define DACR_PORT_SZ_16 (2<<4) 40*4882a593Smuzhiyun #define DACR_IMRS_INIT_CMD (1<<6) 41*4882a593Smuzhiyun #define DACR_CMD_PIN(x) ((x&7)<<8) 42*4882a593Smuzhiyun #define DACR_CASL(x) ((x&3)<<12) 43*4882a593Smuzhiyun #define DACR_RE (1<<15) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Bit definitions and macros for CSCR */ 46*4882a593Smuzhiyun #define CSCR_BSTW 0x08 47*4882a593Smuzhiyun #define CSCR_BSTR 0x10 48*4882a593Smuzhiyun #define CSCR_BEM 0x20 49*4882a593Smuzhiyun #define CSCR_PS(x) ((x&0x3)<<6) 50*4882a593Smuzhiyun #define CSCR_AA 0x100 51*4882a593Smuzhiyun #define CSCR_WS ((x&0xf)<<10) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Bit definitions for the ICR family of registers */ 54*4882a593Smuzhiyun #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ 55*4882a593Smuzhiyun #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ 56*4882a593Smuzhiyun #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ 57*4882a593Smuzhiyun #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ 58*4882a593Smuzhiyun #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ 59*4882a593Smuzhiyun #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ 60*4882a593Smuzhiyun #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ 61*4882a593Smuzhiyun #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ 62*4882a593Smuzhiyun #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ 65*4882a593Smuzhiyun #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ 66*4882a593Smuzhiyun #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ 67*4882a593Smuzhiyun #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* mcf5307_h */ 70*4882a593Smuzhiyun 71