1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * m5301x.h -- Definitions for Freescale Coldfire 5301x 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef m5301x_h 11*4882a593Smuzhiyun #define m5301x_h 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* *** System Control Module (SCM) *** */ 14*4882a593Smuzhiyun #define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) 15*4882a593Smuzhiyun #define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) 16*4882a593Smuzhiyun #define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) 17*4882a593Smuzhiyun #define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12) 18*4882a593Smuzhiyun #define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8) 19*4882a593Smuzhiyun #define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4) 20*4882a593Smuzhiyun #define MPROT_MTR 4 21*4882a593Smuzhiyun #define MPROT_MTW 2 22*4882a593Smuzhiyun #define MPROT_MPL 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) 25*4882a593Smuzhiyun #define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) 26*4882a593Smuzhiyun #define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) 27*4882a593Smuzhiyun #define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) 30*4882a593Smuzhiyun #define SCM_PACRB_PACR13(x) (((x) & 0x0F) << 8) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) 33*4882a593Smuzhiyun #define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) 34*4882a593Smuzhiyun #define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) 35*4882a593Smuzhiyun #define SCM_PACRC_PACR19(x) (((x) & 0x0F) << 16) 36*4882a593Smuzhiyun #define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8) 37*4882a593Smuzhiyun #define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4) 38*4882a593Smuzhiyun #define SCM_PACRC_PACR23(x) ((x) & 0x0F) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28) 41*4882a593Smuzhiyun #define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24) 42*4882a593Smuzhiyun #define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20) 43*4882a593Smuzhiyun #define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12) 44*4882a593Smuzhiyun #define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8) 45*4882a593Smuzhiyun #define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4) 46*4882a593Smuzhiyun #define SCM_PACRD_PACR31(x) ((x) & 0x0F) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28) 49*4882a593Smuzhiyun #define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24) 50*4882a593Smuzhiyun #define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20) 51*4882a593Smuzhiyun #define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16) 52*4882a593Smuzhiyun #define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12) 53*4882a593Smuzhiyun #define SCM_PACRE_PACR37(x) (((x) & 0x0F) << 8) 54*4882a593Smuzhiyun #define SCM_PACRE_PACR39(x) ((x) & 0x0F) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28) 57*4882a593Smuzhiyun #define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24) 58*4882a593Smuzhiyun #define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20) 59*4882a593Smuzhiyun #define SCM_PACRF_PACR43(x) (((x) & 0x0F) << 16) 60*4882a593Smuzhiyun #define SCM_PACRF_PACR44(x) (((x) & 0x0F) << 12) 61*4882a593Smuzhiyun #define SCM_PACRF_PACR45(x) (((x) & 0x0F) << 8) 62*4882a593Smuzhiyun #define SCM_PACRF_PACR46(x) (((x) & 0x0F) << 4) 63*4882a593Smuzhiyun #define SCM_PACRF_PACR47(x) ((x) & 0x0F) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define SCM_PACRG_PACR48(x) (((x) & 0x0F) << 28) 66*4882a593Smuzhiyun #define SCM_PACRG_PACR49(x) (((x) & 0x0F) << 24) 67*4882a593Smuzhiyun #define SCM_PACRG_PACR50(x) (((x) & 0x0F) << 20) 68*4882a593Smuzhiyun #define SCM_PACRG_PACR51(x) (((x) & 0x0F) << 16) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define PACR_SP 4 71*4882a593Smuzhiyun #define PACR_WP 2 72*4882a593Smuzhiyun #define PACR_TP 1 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define SCM_CWCR_RO (0x8000) 75*4882a593Smuzhiyun #define SCM_CWCR_CWR_WH (0x0100) 76*4882a593Smuzhiyun #define SCM_CWCR_CWE (0x0080) 77*4882a593Smuzhiyun #define SCM_CWCR_CWRI_WINDOW (0x0060) 78*4882a593Smuzhiyun #define SCM_CWCR_CWRI_RESET (0x0040) 79*4882a593Smuzhiyun #define SCM_CWCR_CWRI_INT_RESET (0x0020) 80*4882a593Smuzhiyun #define SCM_CWCR_CWRI_INT (0x0000) 81*4882a593Smuzhiyun #define SCM_CWCR_CWT(x) (((x) & 0x001F)) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define SCM_ISR_CFEI (0x02) 84*4882a593Smuzhiyun #define SCM_ISR_CWIC (0x01) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define BCR_GBR (0x00000200) 87*4882a593Smuzhiyun #define BCR_GBW (0x00000100) 88*4882a593Smuzhiyun #define BCR_S7 (0x00000080) 89*4882a593Smuzhiyun #define BCR_S6 (0x00000040) 90*4882a593Smuzhiyun #define BCR_S4 (0x00000010) 91*4882a593Smuzhiyun #define BCR_S1 (0x00000002) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define SCM_CFIER_ECFEI (0x01) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define SCM_CFLOC_LOC (0x80) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define SCM_CFATR_WRITE (0x80) 98*4882a593Smuzhiyun #define SCM_CFATR_SZ32 (0x20) 99*4882a593Smuzhiyun #define SCM_CFATR_SZ16 (0x10) 100*4882a593Smuzhiyun #define SCM_CFATR_SZ08 (0x00) 101*4882a593Smuzhiyun #define SCM_CFATR_CACHE (0x08) 102*4882a593Smuzhiyun #define SCM_CFATR_MODE (0x02) 103*4882a593Smuzhiyun #define SCM_CFATR_TYPE (0x01) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* *** Interrupt Controller (INTC) *** */ 106*4882a593Smuzhiyun #define INT0_LO_RSVD0 (0) 107*4882a593Smuzhiyun #define INT0_LO_EPORT1 (1) 108*4882a593Smuzhiyun #define INT0_LO_EPORT2 (2) 109*4882a593Smuzhiyun #define INT0_LO_EPORT3 (3) 110*4882a593Smuzhiyun #define INT0_LO_EPORT4 (4) 111*4882a593Smuzhiyun #define INT0_LO_EPORT5 (5) 112*4882a593Smuzhiyun #define INT0_LO_EPORT6 (6) 113*4882a593Smuzhiyun #define INT0_LO_EPORT7 (7) 114*4882a593Smuzhiyun #define INT0_LO_EDMA_00 (8) 115*4882a593Smuzhiyun #define INT0_LO_EDMA_01 (9) 116*4882a593Smuzhiyun #define INT0_LO_EDMA_02 (10) 117*4882a593Smuzhiyun #define INT0_LO_EDMA_03 (11) 118*4882a593Smuzhiyun #define INT0_LO_EDMA_04 (12) 119*4882a593Smuzhiyun #define INT0_LO_EDMA_05 (13) 120*4882a593Smuzhiyun #define INT0_LO_EDMA_06 (14) 121*4882a593Smuzhiyun #define INT0_LO_EDMA_07 (15) 122*4882a593Smuzhiyun #define INT0_LO_EDMA_08 (16) 123*4882a593Smuzhiyun #define INT0_LO_EDMA_09 (17) 124*4882a593Smuzhiyun #define INT0_LO_EDMA_10 (18) 125*4882a593Smuzhiyun #define INT0_LO_EDMA_11 (19) 126*4882a593Smuzhiyun #define INT0_LO_EDMA_12 (20) 127*4882a593Smuzhiyun #define INT0_LO_EDMA_13 (21) 128*4882a593Smuzhiyun #define INT0_LO_EDMA_14 (22) 129*4882a593Smuzhiyun #define INT0_LO_EDMA_15 (23) 130*4882a593Smuzhiyun #define INT0_LO_EDMA_ERR (24) 131*4882a593Smuzhiyun #define INT0_LO_SCM_CWIC (25) 132*4882a593Smuzhiyun #define INT0_LO_UART0 (26) 133*4882a593Smuzhiyun #define INT0_LO_UART1 (27) 134*4882a593Smuzhiyun #define INT0_LO_UART2 (28) 135*4882a593Smuzhiyun #define INT0_LO_RSVD1 (29) 136*4882a593Smuzhiyun #define INT0_LO_I2C (30) 137*4882a593Smuzhiyun #define INT0_LO_DSPI (31) 138*4882a593Smuzhiyun #define INT0_HI_DTMR0 (32) 139*4882a593Smuzhiyun #define INT0_HI_DTMR1 (33) 140*4882a593Smuzhiyun #define INT0_HI_DTMR2 (34) 141*4882a593Smuzhiyun #define INT0_HI_DTMR3 (35) 142*4882a593Smuzhiyun #define INT0_HI_FEC0_TXF (36) 143*4882a593Smuzhiyun #define INT0_HI_FEC0_TXB (37) 144*4882a593Smuzhiyun #define INT0_HI_FEC0_UN (38) 145*4882a593Smuzhiyun #define INT0_HI_FEC0_RL (39) 146*4882a593Smuzhiyun #define INT0_HI_FEC0_RXF (40) 147*4882a593Smuzhiyun #define INT0_HI_FEC0_RXB (41) 148*4882a593Smuzhiyun #define INT0_HI_FEC0_MII (42) 149*4882a593Smuzhiyun #define INT0_HI_FEC0_LC (43) 150*4882a593Smuzhiyun #define INT0_HI_FEC0_HBERR (44) 151*4882a593Smuzhiyun #define INT0_HI_FEC0_GRA (45) 152*4882a593Smuzhiyun #define INT0_HI_FEC0_EBERR (46) 153*4882a593Smuzhiyun #define INT0_HI_FEC0_BABT (47) 154*4882a593Smuzhiyun #define INT0_HI_FEC0_BABR (48) 155*4882a593Smuzhiyun #define INT0_HI_FEC1_TXF (49) 156*4882a593Smuzhiyun #define INT0_HI_FEC1_TXB (50) 157*4882a593Smuzhiyun #define INT0_HI_FEC1_UN (51) 158*4882a593Smuzhiyun #define INT0_HI_FEC1_RL (52) 159*4882a593Smuzhiyun #define INT0_HI_FEC1_RXF (53) 160*4882a593Smuzhiyun #define INT0_HI_FEC1_RXB (54) 161*4882a593Smuzhiyun #define INT0_HI_FEC1_MII (55) 162*4882a593Smuzhiyun #define INT0_HI_FEC1_LC (56) 163*4882a593Smuzhiyun #define INT0_HI_FEC1_HBERR (57) 164*4882a593Smuzhiyun #define INT0_HI_FEC1_GRA (58) 165*4882a593Smuzhiyun #define INT0_HI_FEC1_EBERR (59) 166*4882a593Smuzhiyun #define INT0_HI_FEC1_BABT (60) 167*4882a593Smuzhiyun #define INT0_HI_FEC1_BABR (61) 168*4882a593Smuzhiyun #define INT0_HI_SCM_CFEI (62) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* 0 - 24 reserved */ 171*4882a593Smuzhiyun #define INT1_LO_EPORT1_FLAG0 (25) 172*4882a593Smuzhiyun #define INT1_LO_EPORT1_FLAG1 (26) 173*4882a593Smuzhiyun #define INT1_LO_EPORT1_FLAG2 (27) 174*4882a593Smuzhiyun #define INT1_LO_EPORT1_FLAG3 (28) 175*4882a593Smuzhiyun #define INT1_LO_EPORT1_FLAG4 (29) 176*4882a593Smuzhiyun #define INT1_LO_EPORT1_FLAG5 (30) 177*4882a593Smuzhiyun #define INT1_LO_EPORT1_FLAG6 (31) 178*4882a593Smuzhiyun #define INT1_LO_EPORT1_FLAG7 (32) 179*4882a593Smuzhiyun #define INT1_HI_DSPI_EOQF (33) 180*4882a593Smuzhiyun #define INT1_HI_DSPI_TFFF (34) 181*4882a593Smuzhiyun #define INT1_HI_DSPI_TCF (35) 182*4882a593Smuzhiyun #define INT1_HI_DSPI_TFUF (36) 183*4882a593Smuzhiyun #define INT1_HI_DSPI_RFDF (37) 184*4882a593Smuzhiyun #define INT1_HI_DSPI_RFOF (38) 185*4882a593Smuzhiyun #define INT1_HI_DSPI_RFOF_TFUF (39) 186*4882a593Smuzhiyun #define INT1_HI_RNG_EI (40) 187*4882a593Smuzhiyun #define INT1_HI_PLL_LOCF (41) 188*4882a593Smuzhiyun #define INT1_HI_PLL_LOLF (42) 189*4882a593Smuzhiyun #define INT1_HI_PIT0 (43) 190*4882a593Smuzhiyun #define INT1_HI_PIT1 (44) 191*4882a593Smuzhiyun #define INT1_HI_PIT2 (45) 192*4882a593Smuzhiyun #define INT1_HI_PIT3 (46) 193*4882a593Smuzhiyun #define INT1_HI_USBOTG_STS (47) 194*4882a593Smuzhiyun #define INT1_HI_USBHOST_STS (48) 195*4882a593Smuzhiyun #define INT1_HI_SSI (49) 196*4882a593Smuzhiyun /* 50 - 51 reserved */ 197*4882a593Smuzhiyun #define INT1_HI_RTC (52) 198*4882a593Smuzhiyun #define INT1_HI_CCM_USBSTAT (53) 199*4882a593Smuzhiyun #define INT1_HI_CODEC_OR (54) 200*4882a593Smuzhiyun #define INT1_HI_CODEC_RF_TE (55) 201*4882a593Smuzhiyun #define INT1_HI_CODEC_ROE (56) 202*4882a593Smuzhiyun #define INT1_HI_CODEC_TUE (57) 203*4882a593Smuzhiyun /* 58 reserved */ 204*4882a593Smuzhiyun #define INT1_HI_SIM1_DATA (59) 205*4882a593Smuzhiyun #define INT1_HI_SIM1_GENERAL (60) 206*4882a593Smuzhiyun /* 61 - 62 reserved */ 207*4882a593Smuzhiyun #define INT1_HI_SDHC (63) 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun /* *** Reset Controller Module (RCM) *** */ 210*4882a593Smuzhiyun #define RCM_RCR_SOFTRST (0x80) 211*4882a593Smuzhiyun #define RCM_RCR_FRCRSTOUT (0x40) 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #define RCM_RSR_SOFT (0x20) 214*4882a593Smuzhiyun #define RCM_RSR_LOC (0x10) 215*4882a593Smuzhiyun #define RCM_RSR_POR (0x08) 216*4882a593Smuzhiyun #define RCM_RSR_EXT (0x04) 217*4882a593Smuzhiyun #define RCM_RSR_WDR_CORE (0x02) 218*4882a593Smuzhiyun #define RCM_RSR_LOL (0x01) 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* *** Chip Configuration Module (CCM) *** */ 221*4882a593Smuzhiyun #define CCM_CCR_CSC (0x0020) 222*4882a593Smuzhiyun #define CCM_CCR_BOOTPS (0x0010) 223*4882a593Smuzhiyun #define CCM_CCR_LOAD (0x0008) 224*4882a593Smuzhiyun #define CCM_CCR_OSC_MODE (0x0004) 225*4882a593Smuzhiyun #define CCM_CCR_SDR_MODE (0x0002) 226*4882a593Smuzhiyun #define CCM_CCR_RESERVED (0x0001) 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun #define CCM_RCON_SDR_32BIT_UNIFIED (0x0012) 229*4882a593Smuzhiyun #define CCM_RCON_DDR_8BIT_SPLIT (0x0010) 230*4882a593Smuzhiyun #define CCM_RCON_SDR_16BIT_UNIFIED (0x0002) 231*4882a593Smuzhiyun #define CCM_RCON_DDR_16BIT_SPLIT (0x0000) 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun #define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) 234*4882a593Smuzhiyun #define CCM_CIR_PRN(x) ((x) & 0x003F) 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define CCM_MISCCR_FECM (0x8000) 237*4882a593Smuzhiyun #define CCM_MISCCR_CDCSRC (0x4000) 238*4882a593Smuzhiyun #define CCM_MISCCR_PLL_LOCK (0x2000) 239*4882a593Smuzhiyun #define CCM_MISCCR_LIMP (0x1000) 240*4882a593Smuzhiyun #define CCM_MISCCR_BME (0x8000) 241*4882a593Smuzhiyun #define CCM_MISCCR_BMT_UNMASK (0xF8FF) 242*4882a593Smuzhiyun #define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) 243*4882a593Smuzhiyun #define CCM_MISCCR_BMT_512 (0x0700) 244*4882a593Smuzhiyun #define CCM_MISCCR_BMT_1024 (0x0600) 245*4882a593Smuzhiyun #define CCM_MISCCR_BMT_2048 (0x0500) 246*4882a593Smuzhiyun #define CCM_MISCCR_BMT_4096 (0x0400) 247*4882a593Smuzhiyun #define CCM_MISCCR_BMT_8192 (0x0300) 248*4882a593Smuzhiyun #define CCM_MISCCR_BMT_16384 (0x0200) 249*4882a593Smuzhiyun #define CCM_MISCCR_BMT_32768 (0x0100) 250*4882a593Smuzhiyun #define CCM_MISCCR_BMT_65536 (0x0000) 251*4882a593Smuzhiyun #define CCM_MISCCR_TIM_DMA (0x0020) 252*4882a593Smuzhiyun #define CCM_MISCCR_SSI_SRC (0x0010) 253*4882a593Smuzhiyun #define CCM_MISCCR_USBH_OC (0x0008) 254*4882a593Smuzhiyun #define CCM_MISCCR_USBO_OC (0x0004) 255*4882a593Smuzhiyun #define CCM_MISCCR_USB_PUE (0x0002) 256*4882a593Smuzhiyun #define CCM_MISCCR_USB_SRC (0x0001) 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun #define CCM_CDR_LPDIV(x) (((x) & 0x0F) << 8) 259*4882a593Smuzhiyun #define CCM_CDR_SSIDIV(x) ((x) & 0xFF) 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #define CCM_UOCSR_DPPD (0x2000) 262*4882a593Smuzhiyun #define CCM_UOCSR_DMPD (0x1000) 263*4882a593Smuzhiyun #define CCM_UOCSR_DRV_VBUS (0x0800) 264*4882a593Smuzhiyun #define CCM_UOCSR_CRG_VBUS (0x0400) 265*4882a593Smuzhiyun #define CCM_UOCSR_DCR_VBUS (0x0200) 266*4882a593Smuzhiyun #define CCM_UOCSR_DPPU (0x0100) 267*4882a593Smuzhiyun #define CCM_UOCSR_AVLD (0x0080) 268*4882a593Smuzhiyun #define CCM_UOCSR_BVLD (0x0040) 269*4882a593Smuzhiyun #define CCM_UOCSR_VVLD (0x0020) 270*4882a593Smuzhiyun #define CCM_UOCSR_SEND (0x0010) 271*4882a593Smuzhiyun #define CCM_UOCSR_PWRFLT (0x0008) 272*4882a593Smuzhiyun #define CCM_UOCSR_WKUP (0x0004) 273*4882a593Smuzhiyun #define CCM_UOCSR_UOMIE (0x0002) 274*4882a593Smuzhiyun #define CCM_UOCSR_XPDE (0x0001) 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun #define CCM_UHCSR_PORTIND(x) (((x) & 0x0003) << 14) 277*4882a593Smuzhiyun #define CCM_UHCSR_DRV_VBUS (0x0010) 278*4882a593Smuzhiyun #define CCM_UHCSR_PWRFLT (0x0008) 279*4882a593Smuzhiyun #define CCM_UHCSR_WKUP (0x0004) 280*4882a593Smuzhiyun #define CCM_UHCSR_UHMIE (0x0002) 281*4882a593Smuzhiyun #define CCM_UHCSR_XPDE (0x0001) 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun #define CCM_CODCR_BGREN (0x8000) 284*4882a593Smuzhiyun #define CCM_CODCR_REGEN (0x0080) 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun #define CCM_MISC2_IGNLL (0x0008) 287*4882a593Smuzhiyun #define CCM_MISC2_DPS (0x0001) 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun /* *** General Purpose I/O (GPIO) *** */ 290*4882a593Smuzhiyun #define GPIO_PDR_FBCTL ((x) & 0x0F) 291*4882a593Smuzhiyun #define GPIO_PDR_BE ((x) & 0x0F) 292*4882a593Smuzhiyun #define GPIO_PDR_CS32 (((x) & 0x03) << 4) 293*4882a593Smuzhiyun #define GPIO_PDR_CS10 (((x) & 0x03) << 4) 294*4882a593Smuzhiyun #define GPIO_PDR_DSPI ((x) & 0x7F) 295*4882a593Smuzhiyun #define GPIO_PDR_FEC0 ((x) & 0x7F) 296*4882a593Smuzhiyun #define GPIO_PDR_FECI2C ((x) & 0x3F) 297*4882a593Smuzhiyun #define GPIO_PDR_SIMP1 ((x) & 0x1F) 298*4882a593Smuzhiyun #define GPIO_PDR_SIMP0 ((x) & 0x1F) 299*4882a593Smuzhiyun #define GPIO_PDR_TIMER ((x) & 0x0F) 300*4882a593Smuzhiyun #define GPIO_PDR_UART ((x) & 0x3F) 301*4882a593Smuzhiyun #define GPIO_PDR_DEBUG (0x01) 302*4882a593Smuzhiyun #define GPIO_PDR_SDHC ((x) & 0x3F) 303*4882a593Smuzhiyun #define GPIO_PDR_SSI ((x) & 0x1F) 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_OE (0x80) 306*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TA (0x40) 307*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_RWB (0x20) 308*4882a593Smuzhiyun #define GPIO_PAR_FBCTL_TS (0x18) 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun #define GPIO_PAR_BE3 (0x40) 311*4882a593Smuzhiyun #define GPIO_PAR_BE2 (0x10) 312*4882a593Smuzhiyun #define GPIO_PAR_BE1 (0x04) 313*4882a593Smuzhiyun #define GPIO_PAR_BE0 (0x01) 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #define GPIO_PAR_CS5 (0x40) 316*4882a593Smuzhiyun #define GPIO_PAR_CS4 (0x10) 317*4882a593Smuzhiyun #define GPIO_PAR_CS1_UNMASK (0xF3) 318*4882a593Smuzhiyun #define GPIO_PAR_CS1_CS1 (0x0C) 319*4882a593Smuzhiyun #define GPIO_PAR_CS1_SDCS1 (0x08) 320*4882a593Smuzhiyun #define GPIO_PAR_CS0_UNMASK (0xFC) 321*4882a593Smuzhiyun #define GPIO_PAR_CS0_CS0 (0x03) 322*4882a593Smuzhiyun #define GPIO_PAR_CS0_CS4 (0x02) 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_SIN_UNMASK (0x3F) 325*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_SIN (0xC0) 326*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_SIN_U2RXD (0x80) 327*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_SOUT_UNMASK (0xCF) 328*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_SOUT (0x30) 329*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20) 330*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_SCK_UNMASK (0xF3) 331*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_SCK (0x0C) 332*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_SCK_U2CTS (0x08) 333*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_PCS0_UNMASK (0xFC) 334*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_PCS0 (0x03) 335*4882a593Smuzhiyun #define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02) 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun #define GPIO_PAR_DSPIL_PCS1_UNMASK (0x3F) 338*4882a593Smuzhiyun #define GPIO_PAR_DSPIL_PCS1 (0xC0) 339*4882a593Smuzhiyun #define GPIO_PAR_DSPIL_PCS2_UNMASK (0xCF) 340*4882a593Smuzhiyun #define GPIO_PAR_DSPIL_PCS2 (0x30) 341*4882a593Smuzhiyun #define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20) 342*4882a593Smuzhiyun #define GPIO_PAR_DSPIL_PCS3_UNMASK (0xF3) 343*4882a593Smuzhiyun #define GPIO_PAR_DSPIL_PCS3 (0x0C) 344*4882a593Smuzhiyun #define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08) 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun #define GPIO_PAR_FEC1_7W_FEC (0x40) 347*4882a593Smuzhiyun #define GPIO_PAR_FEC1_RMII_FEC (0x10) 348*4882a593Smuzhiyun #define GPIO_PAR_FEC0_7W_FEC (0x04) 349*4882a593Smuzhiyun #define GPIO_PAR_FEC0_RMII_FEC (0x01) 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun /* GPIO_PAR_FECI2C */ 352*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_RMII0_UNMASK (0x3F) 353*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC0 (0x80) 354*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO0 (0x40) 355*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_RMII1_UNMASK (0xCF) 356*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDC1 (0x20) 357*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_MDIO1 (0x10) 358*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_UNMASK (0xF3) 359*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2) 360*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_SDA (0x0C) 361*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_U2TXD (0x08) 362*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04) 363*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_UNMASK (0xFC) 364*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03) 365*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_SCL (0x03) 366*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_U2RXD (0x02) 367*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_MDC1 (0x01) 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun #define GPIO_PAR_IRQ0H_IRQ07_UNMASK (0x3F) 370*4882a593Smuzhiyun #define GPIO_PAR_IRQ0H_IRQ06_UNMASK (0xCF) 371*4882a593Smuzhiyun #define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10) 372*4882a593Smuzhiyun #define GPIO_PAR_IRQ0H_IRQ04_UNMASK (0xFC) 373*4882a593Smuzhiyun #define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02) 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun #define GPIO_PAR_IRQ0L_IRQ01_UNMASK (0xF3) 376*4882a593Smuzhiyun #define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08) 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun #define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40) 379*4882a593Smuzhiyun #define GPIO_PAR_IRQ1H_IRQ16_DDATA2 (0x10) 380*4882a593Smuzhiyun #define GPIO_PAR_IRQ1H_IRQ15_DDATA1 (0x04) 381*4882a593Smuzhiyun #define GPIO_PAR_IRQ1H_IRQ14_DDATA0 (0x01) 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun #define GPIO_PAR_IRQ1L_IRQ13_PST3 (0x40) 384*4882a593Smuzhiyun #define GPIO_PAR_IRQ1L_IRQ12_PST2 (0x10) 385*4882a593Smuzhiyun #define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04) 386*4882a593Smuzhiyun #define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01) 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_DATA1_UNMASK (0x3F) 389*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0) 390*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80) 391*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40) 392*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_VEN1_UNMASK (0xCF) 393*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30) 394*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20) 395*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10) 396*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_RST1_UNMASK (0xF3) 397*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C) 398*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08) 399*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04) 400*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_PD1_UNMASK (0xFC) 401*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03) 402*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02) 403*4882a593Smuzhiyun #define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01) 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun #define GPIO_PAR_SIMP1L_CLK_UNMASK (0x3F) 406*4882a593Smuzhiyun #define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0) 407*4882a593Smuzhiyun #define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80) 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun #define GPIO_PAR_SIMP0_DATA0 (0x10) 410*4882a593Smuzhiyun #define GPIO_PAR_SIMP0_VEN0 (0x08) 411*4882a593Smuzhiyun #define GPIO_PAR_SIMP0_RST0 (0x04) 412*4882a593Smuzhiyun #define GPIO_PAR_SIMP0_PD0 (0x02) 413*4882a593Smuzhiyun #define GPIO_PAR_SIMP0_CLK0 (0x01) 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun #define GPIO_PAR_TIN3(x) (((x) & 0x03) << 6) 416*4882a593Smuzhiyun #define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4) 417*4882a593Smuzhiyun #define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2) 418*4882a593Smuzhiyun #define GPIO_PAR_TIN0(x) ((x) & 0x03) 419*4882a593Smuzhiyun #define GPIO_PAR_TIN3_UNMASK (0x3F) 420*4882a593Smuzhiyun #define GPIO_PAR_TIN3_TIN3 (0xC0) 421*4882a593Smuzhiyun #define GPIO_PAR_TIN3_TOUT3 (0x80) 422*4882a593Smuzhiyun #define GPIO_PAR_TIN3_IRQ03 (0x40) 423*4882a593Smuzhiyun #define GPIO_PAR_TIN2_UNMASK (0xCF) 424*4882a593Smuzhiyun #define GPIO_PAR_TIN2_TIN2 (0x30) 425*4882a593Smuzhiyun #define GPIO_PAR_TIN2_TOUT2 (0x20) 426*4882a593Smuzhiyun #define GPIO_PAR_TIN2_IRQ02 (0x10) 427*4882a593Smuzhiyun #define GPIO_PAR_TIN1_UNMASK (0xF3) 428*4882a593Smuzhiyun #define GPIO_PAR_TIN1_TIN1 (0x0C) 429*4882a593Smuzhiyun #define GPIO_PAR_TIN1_TOUT1 (0x08) 430*4882a593Smuzhiyun #define GPIO_PAR_TIN1_DACK1 (0x04) 431*4882a593Smuzhiyun #define GPIO_PAR_TIN0_UNMASK (0xFC) 432*4882a593Smuzhiyun #define GPIO_PAR_TIN0_TIN0 (0x03) 433*4882a593Smuzhiyun #define GPIO_PAR_TIN0_TOUT0 (0x02) 434*4882a593Smuzhiyun #define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01) 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun #define GPIO_PAR_UART_U2TXD (0x80) 437*4882a593Smuzhiyun #define GPIO_PAR_UART_U2RXD (0x40) 438*4882a593Smuzhiyun #define GPIO_PAR_UART_U0TXD (0x20) 439*4882a593Smuzhiyun #define GPIO_PAR_UART_U0RXD (0x10) 440*4882a593Smuzhiyun #define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2) 441*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS0(x) ((x) & 0x03) 442*4882a593Smuzhiyun #define GPIO_PAR_UART_RTS0_UNMASK (0xF3) 443*4882a593Smuzhiyun #define GPIO_PAR_UART_RTS0_U0RTS (0x0C) 444*4882a593Smuzhiyun #define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08) 445*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS0_UNMASK (0xFC) 446*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS0_U0CTS (0x03) 447*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02) 448*4882a593Smuzhiyun #define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01) 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun #define GPIO_PAR_DEBUG_ALLPST (0x80) 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun #define GPIO_PAR_SDHC_DATA3 (0x20) 453*4882a593Smuzhiyun #define GPIO_PAR_SDHC_DATA2 (0x10) 454*4882a593Smuzhiyun #define GPIO_PAR_SDHC_DATA1 (0x08) 455*4882a593Smuzhiyun #define GPIO_PAR_SDHC_DATA0 (0x04) 456*4882a593Smuzhiyun #define GPIO_PAR_SDHC_CMD (0x02) 457*4882a593Smuzhiyun #define GPIO_PAR_SDHC_CLK (0x01) 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun #define GPIO_PAR_SSIH_RXD(x) (((x) & 0x03) << 6) 460*4882a593Smuzhiyun #define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4) 461*4882a593Smuzhiyun #define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2) 462*4882a593Smuzhiyun #define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03) 463*4882a593Smuzhiyun #define GPIO_PAR_SSIH_RXD_UNMASK (0x3F) 464*4882a593Smuzhiyun #define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0) 465*4882a593Smuzhiyun #define GPIO_PAR_SSIH_RXD_U1RXD (0x40) 466*4882a593Smuzhiyun #define GPIO_PAR_SSIH_TXD_UNMASK (0xCF) 467*4882a593Smuzhiyun #define GPIO_PAR_SSIH_TXD_SSIRXD (0x30) 468*4882a593Smuzhiyun #define GPIO_PAR_SSIH_TXD_U1TXD (0x10) 469*4882a593Smuzhiyun #define GPIO_PAR_SSIH_FS_UNMASK (0xF3) 470*4882a593Smuzhiyun #define GPIO_PAR_SSIH_FS_SSIFS (0x0C) 471*4882a593Smuzhiyun #define GPIO_PAR_SSIH_FS_U1RTS (0x04) 472*4882a593Smuzhiyun #define GPIO_PAR_SSIH_MCLK_UNMASK (0xFC) 473*4882a593Smuzhiyun #define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03) 474*4882a593Smuzhiyun #define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01) 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun #define GPIO_PAR_SSIL_UNMASK (0x3F) 477*4882a593Smuzhiyun #define GPIO_PAR_SSIL_BCLK (0xC0) 478*4882a593Smuzhiyun #define GPIO_PAR_SSIL_U1CTS (0x40) 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun #define GPIO_MSCR_MSCR1(x) (((x) & 0x07) << 5) 481*4882a593Smuzhiyun #define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5) 482*4882a593Smuzhiyun #define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5) 483*4882a593Smuzhiyun #define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5) 484*4882a593Smuzhiyun #define GPIO_MSCR_MSCRn_UNMASK (0x1F) 485*4882a593Smuzhiyun #define GPIO_MSCR_MSCRn_SDR (0xE0) 486*4882a593Smuzhiyun #define GPIO_MSCR_MSCRn_25VDDR (0x60) 487*4882a593Smuzhiyun #define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20) 488*4882a593Smuzhiyun #define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00) 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun #define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2) 491*4882a593Smuzhiyun #define GPIO_MSCR_MSCR5_UNMASK (0xE3) 492*4882a593Smuzhiyun #define GPIO_MSCR_MSCR5_SDR (0x1C) 493*4882a593Smuzhiyun #define GPIO_MSCR_MSCR5_25VDDR (0x0C) 494*4882a593Smuzhiyun #define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04) 495*4882a593Smuzhiyun #define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00) 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun #define GPIO_SRCR_DSPI_UNMASK (0xFC) 498*4882a593Smuzhiyun #define GPIO_SRCR_DSPI(x) ((x) & 0x03) 499*4882a593Smuzhiyun #define GPIO_SRCR_I2C_UNMASK (0xFC) 500*4882a593Smuzhiyun #define GPIO_SRCR_I2C(x) ((x) & 0x03) 501*4882a593Smuzhiyun #define GPIO_SRCR_IRQ_IRQ0_UNMASK (0xF3) 502*4882a593Smuzhiyun #define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2) 503*4882a593Smuzhiyun #define GPIO_SRCR_IRQ_IRQ1DBG_UNMASK (0xFC) 504*4882a593Smuzhiyun #define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03) 505*4882a593Smuzhiyun #define GPIO_SRCR_SIM_SIMP0_UNMASK (0xF3) 506*4882a593Smuzhiyun #define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2) 507*4882a593Smuzhiyun #define GPIO_SRCR_SIM_SIMP1_UNMASK (0xFC) 508*4882a593Smuzhiyun #define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03) 509*4882a593Smuzhiyun #define GPIO_SRCR_TIMER_UNMASK (0xFC) 510*4882a593Smuzhiyun #define GPIO_SRCR_TIMER(x) ((x) & 0x03) 511*4882a593Smuzhiyun #define GPIO_SRCR_UART2_UNMASK (0xF3) 512*4882a593Smuzhiyun #define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2) 513*4882a593Smuzhiyun #define GPIO_SRCR_UART0_UNMASK (0xFC) 514*4882a593Smuzhiyun #define GPIO_SRCR_UART0(x) ((x) & 0x03) 515*4882a593Smuzhiyun #define GPIO_SRCR_SDHC_UNMASK (0xFC) 516*4882a593Smuzhiyun #define GPIO_SRCR_SDHC(x) ((x) & 0x03) 517*4882a593Smuzhiyun #define GPIO_SRCR_SSI_UNMASK (0xFC) 518*4882a593Smuzhiyun #define GPIO_SRCR_SSI(x) ((x) & 0x03) 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun #define SRCR_HIGHEST (0x03) 521*4882a593Smuzhiyun #define SRCR_HIGH (0x02) 522*4882a593Smuzhiyun #define SRCR_LOW (0x01) 523*4882a593Smuzhiyun #define SRCR_LOWEST (0x00) 524*4882a593Smuzhiyun 525*4882a593Smuzhiyun #define GPIO_DSCR_FEC_RMIICLK_UNMASK (0xCF) 526*4882a593Smuzhiyun #define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4) 527*4882a593Smuzhiyun #define GPIO_DSCR_FEC_RMII0_UNMASK (0xF3) 528*4882a593Smuzhiyun #define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2) 529*4882a593Smuzhiyun #define GPIO_DSCR_FEC_RMII1_UNMASK (0xFC) 530*4882a593Smuzhiyun #define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03) 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun #define DSCR_50PF (0x03) 533*4882a593Smuzhiyun #define DSCR_30PF (0x02) 534*4882a593Smuzhiyun #define DSCR_20PF (0x01) 535*4882a593Smuzhiyun #define DSCR_10PF (0x00) 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun #define GPIO_PCRH_DSPI_PCS0_PULLUP_EN (0x80) 538*4882a593Smuzhiyun #define GPIO_PCRH_SIM_VEN1_PULLUP_EN (0x40) 539*4882a593Smuzhiyun #define GPIO_PCRH_SIM_VEN1_PULLUP (0x20) 540*4882a593Smuzhiyun #define GPIO_PCRH_SIM_DATA1_PULLUP_EN (0x10) 541*4882a593Smuzhiyun #define GPIO_PCRH_SIM_DATA1_PULLUP (0x08) 542*4882a593Smuzhiyun #define GPIO_PCRH_SSI_PULLUP_EN (0x02) 543*4882a593Smuzhiyun #define GPIO_PCRH_SSI_PULLUP (0x01) 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun #define GPIO_PCRL_SDHC_DATA3_PULLUP_EN (0x80) 546*4882a593Smuzhiyun #define GPIO_PCRL_SDHC_DATA3_PULLUP (0x40) 547*4882a593Smuzhiyun #define GPIO_PCRL_SDHC_DATA2_PULLUP_EN (0x20) 548*4882a593Smuzhiyun #define GPIO_PCRL_SDHC_DATA1_PULLUP_EN (0x10) 549*4882a593Smuzhiyun #define GPIO_PCRL_SDHC_DATA0_PULLUP_EN (0x08) 550*4882a593Smuzhiyun #define GPIO_PCRL_SDHC_CMD_PULLUP_EN (0x04) 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun /* *** Phase Locked Loop (PLL) *** */ 553*4882a593Smuzhiyun #define PLL_PCR_LOC_IRQ (0x00040000) 554*4882a593Smuzhiyun #define PLL_PCR_LOC_RE (0x00020000) 555*4882a593Smuzhiyun #define PLL_PCR_LOC_EN (0x00010000) 556*4882a593Smuzhiyun #define PLL_PCR_LOL_IRQ (0x00004000) 557*4882a593Smuzhiyun #define PLL_PCR_LOL_RE (0x00002000) 558*4882a593Smuzhiyun #define PLL_PCR_LOL_EN (0x00001000) 559*4882a593Smuzhiyun #define PLL_PCR_REFDIV_UNMASK (0xFFFFF8FF) 560*4882a593Smuzhiyun #define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8) 561*4882a593Smuzhiyun #define PLL_PCR_FBDIV_UNMASK (0xFFFFFFC0) 562*4882a593Smuzhiyun #define PLL_PCR_FBDIV(x) ((x) & 0x3F) 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun #define PLL_PDR_OUTDIV4_UNMASK (0x0FFF) 565*4882a593Smuzhiyun #define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12) 566*4882a593Smuzhiyun #define PLL_PDR_OUTDIV3_UNMASK (0xF0FF) 567*4882a593Smuzhiyun #define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8) 568*4882a593Smuzhiyun #define PLL_PDR_OUTDIV2_UNMASK (0xFF0F) 569*4882a593Smuzhiyun #define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4) 570*4882a593Smuzhiyun #define PLL_PDR_OUTDIV1_UNMASK (0xFFF0) 571*4882a593Smuzhiyun #define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F) 572*4882a593Smuzhiyun #define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x) 573*4882a593Smuzhiyun #define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x) 574*4882a593Smuzhiyun #define PLL_PDR_FB(x) PLL_PDR_OUTDIV2(x) 575*4882a593Smuzhiyun #define PLL_PDR_CPU(x) PLL_PDR_OUTDIV1(x) 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun #define PLL_PSR_LOCF (0x00000200) 578*4882a593Smuzhiyun #define PLL_PSR_LOC (0x00000100) 579*4882a593Smuzhiyun #define PLL_PSR_LOLF (0x00000040) 580*4882a593Smuzhiyun #define PLL_PSR_LOCKS (0x00000020) 581*4882a593Smuzhiyun #define PLL_PSR_LOCK (0x00000010) 582*4882a593Smuzhiyun #define PLL_PSR_MODE(x) ((x) & 0x07) 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun /* *** Real Time Clock *** */ 585*4882a593Smuzhiyun #define RTC_OCEN_OSCBYP (0x00000010) 586*4882a593Smuzhiyun #define RTC_OCEN_CLKEN (0x00000008) 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun /* SDRAM */ 589*4882a593Smuzhiyun #define SDRAMC_SDCR_CKE (0x40000000) 590*4882a593Smuzhiyun #define SDRAMC_SDCR_REF (0x10000000) 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun #endif /* m5301x_h */ 593