1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef m5253_h 9*4882a593Smuzhiyun #define m5253_h 10*4882a593Smuzhiyun /****************************************************************************/ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * PLL Module (PLL) 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Register read/write macros */ 17*4882a593Smuzhiyun #define PLL_PLLCR (0x000180) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define SIM_RSR (0x000000) 20*4882a593Smuzhiyun #define SIM_SYPCR (0x000001) 21*4882a593Smuzhiyun #define SIM_SWIVR (0x000002) 22*4882a593Smuzhiyun #define SIM_SWSR (0x000003) 23*4882a593Smuzhiyun #define SIM_MPARK (0x00000C) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Bit definitions and macros for RSR */ 26*4882a593Smuzhiyun #define SIM_RSR_SWTR (0x20) 27*4882a593Smuzhiyun #define SIM_RSR_HRST (0x80) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Register read/write macros */ 30*4882a593Smuzhiyun #define CIM_MISCCR (0x000500) 31*4882a593Smuzhiyun #define CIM_ATA_DADDR (0x000504) 32*4882a593Smuzhiyun #define CIM_ATA_DCOUNT (0x000508) 33*4882a593Smuzhiyun #define CIM_RTC_TIME (0x00050C) 34*4882a593Smuzhiyun #define CIM_USB_CANCLK (0x000510) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Bit definitions and macros for MISCCR */ 37*4882a593Smuzhiyun #define CIM_MISCCR_ADTA (0x00000001) 38*4882a593Smuzhiyun #define CIM_MISCCR_ADTD (0x00000002) 39*4882a593Smuzhiyun #define CIM_MISCCR_ADIE (0x00000004) 40*4882a593Smuzhiyun #define CIM_MISCCR_ADIC (0x00000008) 41*4882a593Smuzhiyun #define CIM_MISCCR_ADIP (0x00000010) 42*4882a593Smuzhiyun #define CIM_MISCCR_CPUEND (0x00000020) 43*4882a593Smuzhiyun #define CIM_MISCCR_DMAEND (0x00000040) 44*4882a593Smuzhiyun #define CIM_MISCCR_RTCCLR (0x00000080) 45*4882a593Smuzhiyun #define CIM_MISCCR_RTCPL (0x00000100) 46*4882a593Smuzhiyun #define CIM_MISCCR_URIE (0x00000800) 47*4882a593Smuzhiyun #define CIM_MISCCR_URIC (0x00001000) 48*4882a593Smuzhiyun #define CIM_MISCCR_URIP (0x00002000) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Bit definitions and macros for ATA_DADDR */ 51*4882a593Smuzhiyun #define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2) 52*4882a593Smuzhiyun #define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Bit definitions and macros for ATA_DCOUNT */ 55*4882a593Smuzhiyun #define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF)) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif /* m5253_h */ 58