1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * mcf5329.h -- Definitions for Freescale Coldfire 5329 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef mcf5235_h 11*4882a593Smuzhiyun #define mcf5235_h 12*4882a593Smuzhiyun /****************************************************************************/ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /********************************************************************* 15*4882a593Smuzhiyun * System Control Module (SCM) 16*4882a593Smuzhiyun *********************************************************************/ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Bit definition and macros for SCM_IPSBAR */ 19*4882a593Smuzhiyun #define SCM_IPSBAR_BA(x) (((x)&0x03)<<30) 20*4882a593Smuzhiyun #define SCM_IPSBAR_V (0x00000001) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Bit definition and macros for SCM_RAMBAR */ 23*4882a593Smuzhiyun #define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16) 24*4882a593Smuzhiyun #define SCM_RAMBAR_BDE (0x00000200) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Bit definition and macros for SCM_CRSR */ 27*4882a593Smuzhiyun #define SCM_CRSR_EXT (0x80) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Bit definitions and macros for SCM_CWCR */ 30*4882a593Smuzhiyun #define SCM_CWCR_CWE (0x80) 31*4882a593Smuzhiyun #define SCM_CWCR_CWRI (0x40) 32*4882a593Smuzhiyun #define SCM_CWCR_CWT(x) (((x)&0x07)<<3) 33*4882a593Smuzhiyun #define SCM_CWCR_CWTA (0x04) 34*4882a593Smuzhiyun #define SCM_CWCR_CWTAVAL (0x02) 35*4882a593Smuzhiyun #define SCM_CWCR_CWTIC (0x01) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Bit definitions and macros for SCM_LPICR */ 38*4882a593Smuzhiyun #define SCM_LPICR_ENBSTOP (0x80) 39*4882a593Smuzhiyun #define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) 40*4882a593Smuzhiyun #define SCM_LPICR_XLPM_IPL_ANY (0x00) 41*4882a593Smuzhiyun #define SCM_LPICR_XLPM_IPL_L2_7 (0x10) 42*4882a593Smuzhiyun #define SCM_LPICR_XLPM_IPL_L3_7 (0x20) 43*4882a593Smuzhiyun #define SCM_LPICR_XLPM_IPL_L4_7 (0x30) 44*4882a593Smuzhiyun #define SCM_LPICR_XLPM_IPL_L5_7 (0x40) 45*4882a593Smuzhiyun #define SCM_LPICR_XLPM_IPL_L6_7 (0x50) 46*4882a593Smuzhiyun #define SCM_LPICR_XLPM_IPL_L7 (0x70) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Bit definitions and macros for SCM_DMAREQC */ 49*4882a593Smuzhiyun #define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16) 50*4882a593Smuzhiyun #define SCM_DMAREQC_EXT_ETPU (0x00080000) 51*4882a593Smuzhiyun #define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000) 52*4882a593Smuzhiyun #define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000) 53*4882a593Smuzhiyun #define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000) 54*4882a593Smuzhiyun #define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12) 55*4882a593Smuzhiyun #define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8) 56*4882a593Smuzhiyun #define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4) 57*4882a593Smuzhiyun #define SCM_DMAREQC_DMAC0(x) (((x)&0x0F)) 58*4882a593Smuzhiyun #define SCM_DMAREQC_DMACn_DTMR0 (0x04) 59*4882a593Smuzhiyun #define SCM_DMAREQC_DMACn_DTMR1 (0x05) 60*4882a593Smuzhiyun #define SCM_DMAREQC_DMACn_DTMR2 (0x06) 61*4882a593Smuzhiyun #define SCM_DMAREQC_DMACn_DTMR3 (0x07) 62*4882a593Smuzhiyun #define SCM_DMAREQC_DMACn_UART0RX (0x08) 63*4882a593Smuzhiyun #define SCM_DMAREQC_DMACn_UART1RX (0x09) 64*4882a593Smuzhiyun #define SCM_DMAREQC_DMACn_UART2RX (0x0A) 65*4882a593Smuzhiyun #define SCM_DMAREQC_DMACn_UART0TX (0x0C) 66*4882a593Smuzhiyun #define SCM_DMAREQC_DMACn_UART1TX (0x0D) 67*4882a593Smuzhiyun #define SCM_DMAREQC_DMACn_UART3TX (0x0E) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Bit definitions and macros for SCM_MPARK */ 70*4882a593Smuzhiyun #define SCM_MPARK_M2_P_EN (0x02000000) 71*4882a593Smuzhiyun #define SCM_MPARK_M3_PRTY_MSK (0x00C00000) 72*4882a593Smuzhiyun #define SCM_MPARK_M3_PRTY_4TH (0x00000000) 73*4882a593Smuzhiyun #define SCM_MPARK_M3_PRTY_3RD (0x00400000) 74*4882a593Smuzhiyun #define SCM_MPARK_M3_PRTY_2ND (0x00800000) 75*4882a593Smuzhiyun #define SCM_MPARK_M3_PRTY_1ST (0x00C00000) 76*4882a593Smuzhiyun #define SCM_MPARK_M2_PRTY_MSK (0x00300000) 77*4882a593Smuzhiyun #define SCM_MPARK_M2_PRTY_4TH (0x00000000) 78*4882a593Smuzhiyun #define SCM_MPARK_M2_PRTY_3RD (0x00100000) 79*4882a593Smuzhiyun #define SCM_MPARK_M2_PRTY_2ND (0x00200000) 80*4882a593Smuzhiyun #define SCM_MPARK_M2_PRTY_1ST (0x00300000) 81*4882a593Smuzhiyun #define SCM_MPARK_M0_PRTY_MSK (0x000C0000) 82*4882a593Smuzhiyun #define SCM_MPARK_M0_PRTY_4TH (0x00000000) 83*4882a593Smuzhiyun #define SCM_MPARK_M0_PRTY_3RD (0x00040000) 84*4882a593Smuzhiyun #define SCM_MPARK_M0_PRTY_2ND (0x00080000) 85*4882a593Smuzhiyun #define SCM_MPARK_M0_PRTY_1ST (0x000C0000) 86*4882a593Smuzhiyun #define SCM_MPARK_FIXED (0x00004000) 87*4882a593Smuzhiyun #define SCM_MPARK_TIMEOUT (0x00002000) 88*4882a593Smuzhiyun #define SCM_MPARK_PRKLAST (0x00001000) 89*4882a593Smuzhiyun #define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* Bit definitions and macros for SCM_MPR */ 92*4882a593Smuzhiyun #define SCM_MPR_MPR3 (0x08) 93*4882a593Smuzhiyun #define SCM_MPR_MPR2 (0x04) 94*4882a593Smuzhiyun #define SCM_MPR_MPR1 (0x02) 95*4882a593Smuzhiyun #define SCM_MPR_MPR0 (0x01) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* Bit definitions and macros for SCM_PACRn */ 98*4882a593Smuzhiyun #define SCM_PACRn_LOCK1 (0x80) 99*4882a593Smuzhiyun #define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4) 100*4882a593Smuzhiyun #define SCM_PACRn_LOCK0 (0x08) 101*4882a593Smuzhiyun #define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Bit definitions and macros for SCM_GPACR */ 104*4882a593Smuzhiyun #define SCM_PACRn_LOCK (0x80) 105*4882a593Smuzhiyun #define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /********************************************************************* 108*4882a593Smuzhiyun * SDRAM Controller (SDRAMC) 109*4882a593Smuzhiyun *********************************************************************/ 110*4882a593Smuzhiyun /* Bit definitions and macros for SDRAMC_DCR */ 111*4882a593Smuzhiyun #define SDRAMC_DCR_NAM (0x2000) 112*4882a593Smuzhiyun #define SDRAMC_DCR_COC (0x1000) 113*4882a593Smuzhiyun #define SDRAMC_DCR_IS (0x0800) 114*4882a593Smuzhiyun #define SDRAMC_DCR_RTIM_MASK (0x0C00) 115*4882a593Smuzhiyun #define SDRAMC_DCR_RTIM_3CLKS (0x0000) 116*4882a593Smuzhiyun #define SDRAMC_DCR_RTIM_6CLKS (0x0200) 117*4882a593Smuzhiyun #define SDRAMC_DCR_RTIM_9CLKS (0x0400) 118*4882a593Smuzhiyun #define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* Bit definitions and macros for SDRAMC_DARCn */ 121*4882a593Smuzhiyun #define SDRAMC_DARCn_BA(x) ((x)&0xFFFC0000) 122*4882a593Smuzhiyun #define SDRAMC_DARCn_RE (0x00008000) 123*4882a593Smuzhiyun #define SDRAMC_DARCn_CASL_MASK (0x00003000) 124*4882a593Smuzhiyun #define SDRAMC_DARCn_CASL_C0 (0x00000000) 125*4882a593Smuzhiyun #define SDRAMC_DARCn_CASL_C1 (0x00001000) 126*4882a593Smuzhiyun #define SDRAMC_DARCn_CASL_C2 (0x00002000) 127*4882a593Smuzhiyun #define SDRAMC_DARCn_CASL_C3 (0x00003000) 128*4882a593Smuzhiyun #define SDRAMC_DARCn_CBM_MASK (0x00000700) 129*4882a593Smuzhiyun #define SDRAMC_DARCn_CBM_CMD17 (0x00000000) 130*4882a593Smuzhiyun #define SDRAMC_DARCn_CBM_CMD18 (0x00000100) 131*4882a593Smuzhiyun #define SDRAMC_DARCn_CBM_CMD19 (0x00000200) 132*4882a593Smuzhiyun #define SDRAMC_DARCn_CBM_CMD20 (0x00000300) 133*4882a593Smuzhiyun #define SDRAMC_DARCn_CBM_CMD21 (0x00000400) 134*4882a593Smuzhiyun #define SDRAMC_DARCn_CBM_CMD22 (0x00000500) 135*4882a593Smuzhiyun #define SDRAMC_DARCn_CBM_CMD23 (0x00000600) 136*4882a593Smuzhiyun #define SDRAMC_DARCn_CBM_CMD24 (0x00000700) 137*4882a593Smuzhiyun #define SDRAMC_DARCn_IMRS (0x00000040) 138*4882a593Smuzhiyun #define SDRAMC_DARCn_PS_MASK (0x00000030) 139*4882a593Smuzhiyun #define SDRAMC_DARCn_PS_32 (0x00000000) 140*4882a593Smuzhiyun #define SDRAMC_DARCn_PS_16 (0x00000010) 141*4882a593Smuzhiyun #define SDRAMC_DARCn_PS_8 (0x00000020) 142*4882a593Smuzhiyun #define SDRAMC_DARCn_IP (0x00000008) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* Bit definitions and macros for SDRAMC_DMRn */ 145*4882a593Smuzhiyun #define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18) 146*4882a593Smuzhiyun #define SDRAMC_DMRn_WP (0x00000100) 147*4882a593Smuzhiyun #define SDRAMC_DMRn_V (0x00000001) 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /********************************************************************* 150*4882a593Smuzhiyun * Interrupt Controller (INTC) 151*4882a593Smuzhiyun *********************************************************************/ 152*4882a593Smuzhiyun #define INT0_LO_RSVD0 (0) 153*4882a593Smuzhiyun #define INT0_LO_EPORT1 (1) 154*4882a593Smuzhiyun #define INT0_LO_EPORT2 (2) 155*4882a593Smuzhiyun #define INT0_LO_EPORT3 (3) 156*4882a593Smuzhiyun #define INT0_LO_EPORT4 (4) 157*4882a593Smuzhiyun #define INT0_LO_EPORT5 (5) 158*4882a593Smuzhiyun #define INT0_LO_EPORT6 (6) 159*4882a593Smuzhiyun #define INT0_LO_EPORT7 (7) 160*4882a593Smuzhiyun #define INT0_LO_SCM (8) 161*4882a593Smuzhiyun #define INT0_LO_DMA0 (9) 162*4882a593Smuzhiyun #define INT0_LO_DMA1 (10) 163*4882a593Smuzhiyun #define INT0_LO_DMA2 (11) 164*4882a593Smuzhiyun #define INT0_LO_DMA3 (12) 165*4882a593Smuzhiyun #define INT0_LO_UART0 (13) 166*4882a593Smuzhiyun #define INT0_LO_UART1 (14) 167*4882a593Smuzhiyun #define INT0_LO_UART2 (15) 168*4882a593Smuzhiyun #define INT0_LO_RSVD1 (16) 169*4882a593Smuzhiyun #define INT0_LO_I2C (17) 170*4882a593Smuzhiyun #define INT0_LO_QSPI (18) 171*4882a593Smuzhiyun #define INT0_LO_DTMR0 (19) 172*4882a593Smuzhiyun #define INT0_LO_DTMR1 (20) 173*4882a593Smuzhiyun #define INT0_LO_DTMR2 (21) 174*4882a593Smuzhiyun #define INT0_LO_DTMR3 (22) 175*4882a593Smuzhiyun #define INT0_LO_FEC_TXF (23) 176*4882a593Smuzhiyun #define INT0_LO_FEC_TXB (24) 177*4882a593Smuzhiyun #define INT0_LO_FEC_UN (25) 178*4882a593Smuzhiyun #define INT0_LO_FEC_RL (26) 179*4882a593Smuzhiyun #define INT0_LO_FEC_RXF (27) 180*4882a593Smuzhiyun #define INT0_LO_FEC_RXB (28) 181*4882a593Smuzhiyun #define INT0_LO_FEC_MII (29) 182*4882a593Smuzhiyun #define INT0_LO_FEC_LC (30) 183*4882a593Smuzhiyun #define INT0_LO_FEC_HBERR (31) 184*4882a593Smuzhiyun #define INT0_HI_FEC_GRA (32) 185*4882a593Smuzhiyun #define INT0_HI_FEC_EBERR (33) 186*4882a593Smuzhiyun #define INT0_HI_FEC_BABT (34) 187*4882a593Smuzhiyun #define INT0_HI_FEC_BABR (35) 188*4882a593Smuzhiyun #define INT0_HI_PIT0 (36) 189*4882a593Smuzhiyun #define INT0_HI_PIT1 (37) 190*4882a593Smuzhiyun #define INT0_HI_PIT2 (38) 191*4882a593Smuzhiyun #define INT0_HI_PIT3 (39) 192*4882a593Smuzhiyun #define INT0_HI_RNG (40) 193*4882a593Smuzhiyun #define INT0_HI_SKHA (41) 194*4882a593Smuzhiyun #define INT0_HI_MDHA (42) 195*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF0I (43) 196*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF1I (44) 197*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF2I (45) 198*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF3I (46) 199*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF4I (47) 200*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF5I (48) 201*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF6I (49) 202*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF7I (50) 203*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF8I (51) 204*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF9I (52) 205*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF10I (53) 206*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF11I (54) 207*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF12I (55) 208*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF13I (56) 209*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF14I (57) 210*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF15I (58) 211*4882a593Smuzhiyun #define INT0_HI_CAN1_ERRINT (59) 212*4882a593Smuzhiyun #define INT0_HI_CAN1_BOFFINT (60) 213*4882a593Smuzhiyun /* 60-63 Reserved */ 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* 0 - 7 Reserved */ 216*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF0I (8) 217*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF1I (9) 218*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF2I (10) 219*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF3I (11) 220*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF4I (12) 221*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF5I (13) 222*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF6I (14) 223*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF7I (15) 224*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF8I (16) 225*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF9I (17) 226*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF10I (18) 227*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF11I (19) 228*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF12I (20) 229*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF13I (21) 230*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF14I (22) 231*4882a593Smuzhiyun #define INT1_LO_CAN1_BUF15I (23) 232*4882a593Smuzhiyun #define INT1_LO_CAN1_ERRINT (24) 233*4882a593Smuzhiyun #define INT1_LO_CAN1_BOFFINT (25) 234*4882a593Smuzhiyun /* 26 Reserved */ 235*4882a593Smuzhiyun #define INT1_LO_ETPU_TC0F (27) 236*4882a593Smuzhiyun #define INT1_LO_ETPU_TC1F (28) 237*4882a593Smuzhiyun #define INT1_LO_ETPU_TC2F (29) 238*4882a593Smuzhiyun #define INT1_LO_ETPU_TC3F (30) 239*4882a593Smuzhiyun #define INT1_LO_ETPU_TC4F (31) 240*4882a593Smuzhiyun #define INT1_HI_ETPU_TC5F (32) 241*4882a593Smuzhiyun #define INT1_HI_ETPU_TC6F (33) 242*4882a593Smuzhiyun #define INT1_HI_ETPU_TC7F (34) 243*4882a593Smuzhiyun #define INT1_HI_ETPU_TC8F (35) 244*4882a593Smuzhiyun #define INT1_HI_ETPU_TC9F (36) 245*4882a593Smuzhiyun #define INT1_HI_ETPU_TC10F (37) 246*4882a593Smuzhiyun #define INT1_HI_ETPU_TC11F (38) 247*4882a593Smuzhiyun #define INT1_HI_ETPU_TC12F (39) 248*4882a593Smuzhiyun #define INT1_HI_ETPU_TC13F (40) 249*4882a593Smuzhiyun #define INT1_HI_ETPU_TC14F (41) 250*4882a593Smuzhiyun #define INT1_HI_ETPU_TC15F (42) 251*4882a593Smuzhiyun #define INT1_HI_ETPU_TC16F (43) 252*4882a593Smuzhiyun #define INT1_HI_ETPU_TC17F (44) 253*4882a593Smuzhiyun #define INT1_HI_ETPU_TC18F (45) 254*4882a593Smuzhiyun #define INT1_HI_ETPU_TC19F (46) 255*4882a593Smuzhiyun #define INT1_HI_ETPU_TC20F (47) 256*4882a593Smuzhiyun #define INT1_HI_ETPU_TC21F (48) 257*4882a593Smuzhiyun #define INT1_HI_ETPU_TC22F (49) 258*4882a593Smuzhiyun #define INT1_HI_ETPU_TC23F (50) 259*4882a593Smuzhiyun #define INT1_HI_ETPU_TC24F (51) 260*4882a593Smuzhiyun #define INT1_HI_ETPU_TC25F (52) 261*4882a593Smuzhiyun #define INT1_HI_ETPU_TC26F (53) 262*4882a593Smuzhiyun #define INT1_HI_ETPU_TC27F (54) 263*4882a593Smuzhiyun #define INT1_HI_ETPU_TC28F (55) 264*4882a593Smuzhiyun #define INT1_HI_ETPU_TC29F (56) 265*4882a593Smuzhiyun #define INT1_HI_ETPU_TC30F (57) 266*4882a593Smuzhiyun #define INT1_HI_ETPU_TC31F (58) 267*4882a593Smuzhiyun #define INT1_HI_ETPU_TGIF (59) 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /********************************************************************* 270*4882a593Smuzhiyun * General Purpose I/O (GPIO) 271*4882a593Smuzhiyun *********************************************************************/ 272*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PODR */ 273*4882a593Smuzhiyun #define GPIO_PODR_ADDR(x) (((x)&0x07)<<5) 274*4882a593Smuzhiyun #define GPIO_PODR_ADDR_MASK (0xE0) 275*4882a593Smuzhiyun #define GPIO_PODR_BS(x) ((x)&0x0F) 276*4882a593Smuzhiyun #define GPIO_PODR_BS_MASK (0x0F) 277*4882a593Smuzhiyun #define GPIO_PODR_CS(x) (((x)&0x7F)<<1) 278*4882a593Smuzhiyun #define GPIO_PODR_CS_MASK (0xFE) 279*4882a593Smuzhiyun #define GPIO_PODR_SDRAM(X) ((x)&0x3F) 280*4882a593Smuzhiyun #define GPIO_PODR_SDRAM_MASK (0x3F) 281*4882a593Smuzhiyun #define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x) 282*4882a593Smuzhiyun #define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK 283*4882a593Smuzhiyun #define GPIO_PODR_UARTH(x) ((x)&0x03) 284*4882a593Smuzhiyun #define GPIO_PODR_UARTH_MASK (0x03) 285*4882a593Smuzhiyun #define GPIO_PODR_QSPI(x) ((x)&0x1F) 286*4882a593Smuzhiyun #define GPIO_PODR_QSPI_MASK (0x1F) 287*4882a593Smuzhiyun #define GPIO_PODR_ETPU(x) ((x)&0x07) 288*4882a593Smuzhiyun #define GPIO_PODR_ETPU_MASK (0x07) 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PDDR */ 291*4882a593Smuzhiyun #define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x) 292*4882a593Smuzhiyun #define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK 293*4882a593Smuzhiyun #define GPIO_PDDR_BS(x) GPIO_PODR_BS(x) 294*4882a593Smuzhiyun #define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK 295*4882a593Smuzhiyun #define GPIO_PDDR_CS(x) GPIO_PODR_CS(x) 296*4882a593Smuzhiyun #define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK 297*4882a593Smuzhiyun #define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X) 298*4882a593Smuzhiyun #define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK 299*4882a593Smuzhiyun #define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x) 300*4882a593Smuzhiyun #define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK 301*4882a593Smuzhiyun #define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x) 302*4882a593Smuzhiyun #define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK 303*4882a593Smuzhiyun #define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x) 304*4882a593Smuzhiyun #define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK 305*4882a593Smuzhiyun #define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x) 306*4882a593Smuzhiyun #define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PPDSDR */ 309*4882a593Smuzhiyun #define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x) 310*4882a593Smuzhiyun #define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK 311*4882a593Smuzhiyun #define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x) 312*4882a593Smuzhiyun #define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK 313*4882a593Smuzhiyun #define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x) 314*4882a593Smuzhiyun #define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK 315*4882a593Smuzhiyun #define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X) 316*4882a593Smuzhiyun #define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK 317*4882a593Smuzhiyun #define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x) 318*4882a593Smuzhiyun #define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK 319*4882a593Smuzhiyun #define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x) 320*4882a593Smuzhiyun #define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK 321*4882a593Smuzhiyun #define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x) 322*4882a593Smuzhiyun #define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK 323*4882a593Smuzhiyun #define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x) 324*4882a593Smuzhiyun #define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PCLRR */ 327*4882a593Smuzhiyun #define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x) 328*4882a593Smuzhiyun #define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK 329*4882a593Smuzhiyun #define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x) 330*4882a593Smuzhiyun #define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK 331*4882a593Smuzhiyun #define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x) 332*4882a593Smuzhiyun #define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK 333*4882a593Smuzhiyun #define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X) 334*4882a593Smuzhiyun #define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK 335*4882a593Smuzhiyun #define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x) 336*4882a593Smuzhiyun #define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK 337*4882a593Smuzhiyun #define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x) 338*4882a593Smuzhiyun #define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK 339*4882a593Smuzhiyun #define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x) 340*4882a593Smuzhiyun #define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK 341*4882a593Smuzhiyun #define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x) 342*4882a593Smuzhiyun #define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_PAR */ 345*4882a593Smuzhiyun #define GPIO_PAR_AD_ADDR23 (0x80) 346*4882a593Smuzhiyun #define GPIO_PAR_AD_ADDR22 (0x40) 347*4882a593Smuzhiyun #define GPIO_PAR_AD_ADDR21 (0x20) 348*4882a593Smuzhiyun #define GPIO_PAR_AD_DATAL (0x01) 349*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_OE (0x4000) 350*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TA (0x1000) 351*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10) 352*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00) 353*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400) 354*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800) 355*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00) 356*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_RWB (0x0100) 357*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TSIZ1 (0x0040) 358*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TSIZ0 (0x0010) 359*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2) 360*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TS_MASK (0x0C) 361*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TS_GPIO (0x04) 362*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TS_DACK2 (0x08) 363*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C) 364*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03) 365*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TIP_MASK (0x03) 366*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TIP_GPIO (0x01) 367*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02) 368*4882a593Smuzhiyun #define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03) 369*4882a593Smuzhiyun #define GPIO_PAR_BS(x) ((x)&0x0F) 370*4882a593Smuzhiyun #define GPIO_PAR_BS_MASK (0x0F) 371*4882a593Smuzhiyun #define GPIO_PAR_CS(x) (((x)&0x7F)<<1) 372*4882a593Smuzhiyun #define GPIO_PAR_CS_MASK (0xFE) 373*4882a593Smuzhiyun #define GPIO_PAR_CS_CS7 (0x80) 374*4882a593Smuzhiyun #define GPIO_PAR_CS_CS6 (0x40) 375*4882a593Smuzhiyun #define GPIO_PAR_CS_CS5 (0x20) 376*4882a593Smuzhiyun #define GPIO_PAR_CS_CS4 (0x10) 377*4882a593Smuzhiyun #define GPIO_PAR_CS_CS3 (0x08) 378*4882a593Smuzhiyun #define GPIO_PAR_CS_CS2 (0x04) 379*4882a593Smuzhiyun #define GPIO_PAR_CS_CS1 (0x02) 380*4882a593Smuzhiyun #define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3 381*4882a593Smuzhiyun #define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2 382*4882a593Smuzhiyun #define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6) 383*4882a593Smuzhiyun #define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0) 384*4882a593Smuzhiyun #define GPIO_PAR_SDRAM_SDWE (0x20) 385*4882a593Smuzhiyun #define GPIO_PAR_SDRAM_SCAS (0x10) 386*4882a593Smuzhiyun #define GPIO_PAR_SDRAM_SRAS (0x08) 387*4882a593Smuzhiyun #define GPIO_PAR_SDRAM_SCKE (0x04) 388*4882a593Smuzhiyun #define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03) 389*4882a593Smuzhiyun #define GPIO_PAR_SDRAM_SDCS_MASK (0x03) 390*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6) 391*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_EMDC_MASK (0xC0) 392*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40) 393*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80) 394*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0) 395*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4) 396*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_EMDIO_MASK (0x30) 397*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10) 398*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20) 399*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30) 400*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) 401*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_MASK (0x0C) 402*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08) 403*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C) 404*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03) 405*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_MASK (0x03) 406*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02) 407*4882a593Smuzhiyun #define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03) 408*4882a593Smuzhiyun #define GPIO_PAR_UART_DREQ2 (0x8000) 409*4882a593Smuzhiyun #define GPIO_PAR_UART_CAN1EN (0x4000) 410*4882a593Smuzhiyun #define GPIO_PAR_UART_U2RXD (0x2000) 411*4882a593Smuzhiyun #define GPIO_PAR_UART_U2TXD (0x1000) 412*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10) 413*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RXD_MASK (0x0C00) 414*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800) 415*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) 416*4882a593Smuzhiyun #define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8) 417*4882a593Smuzhiyun #define GPIO_PAR_UART_U1TXD_MASK (0x0300) 418*4882a593Smuzhiyun #define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200) 419*4882a593Smuzhiyun #define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) 420*4882a593Smuzhiyun #define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6) 421*4882a593Smuzhiyun #define GPIO_PAR_UART_U1CTS_MASK (0x00C0) 422*4882a593Smuzhiyun #define GPIO_PAR_UART_U1CTS_U2CTS (0x0080) 423*4882a593Smuzhiyun #define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0) 424*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4) 425*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RTS_MASK (0x0030) 426*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RTS_U2RTS (0x0020) 427*4882a593Smuzhiyun #define GPIO_PAR_UART_U1RTS_U1RTS (0x0030) 428*4882a593Smuzhiyun #define GPIO_PAR_UART_U0RXD (0x0008) 429*4882a593Smuzhiyun #define GPIO_PAR_UART_U0TXD (0x0004) 430*4882a593Smuzhiyun #define GPIO_PAR_UART_U0CTS (0x0002) 431*4882a593Smuzhiyun #define GPIO_PAR_UART_U0RTS (0x0001) 432*4882a593Smuzhiyun #define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6) 433*4882a593Smuzhiyun #define GPIO_PAR_QSPI_CS1_MASK (0xC0) 434*4882a593Smuzhiyun #define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80) 435*4882a593Smuzhiyun #define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0) 436*4882a593Smuzhiyun #define GPIO_PAR_QSPI_CS0 (0x20) 437*4882a593Smuzhiyun #define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3) 438*4882a593Smuzhiyun #define GPIO_PAR_QSPI_DIN_MASK (0x18) 439*4882a593Smuzhiyun #define GPIO_PAR_QSPI_DIN_I2CSDA (0x10) 440*4882a593Smuzhiyun #define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18) 441*4882a593Smuzhiyun #define GPIO_PAR_QSPI_DOUT (0x04) 442*4882a593Smuzhiyun #define GPIO_PAR_QSPI_SCK(x) ((x)&0x03) 443*4882a593Smuzhiyun #define GPIO_PAR_QSPI_SCK_MASK (0x03) 444*4882a593Smuzhiyun #define GPIO_PAR_QSPI_SCK_I2CSCL (0x02) 445*4882a593Smuzhiyun #define GPIO_PAR_QSPI_SCK_QSPISCK (0x03) 446*4882a593Smuzhiyun #define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14) 447*4882a593Smuzhiyun #define GPIO_PAR_DT3IN_MASK (0xC000) 448*4882a593Smuzhiyun #define GPIO_PAR_DT3IN_QSPICS2 (0x4000) 449*4882a593Smuzhiyun #define GPIO_PAR_DT3IN_U2CTS (0x8000) 450*4882a593Smuzhiyun #define GPIO_PAR_DT3IN_DT3IN (0xC000) 451*4882a593Smuzhiyun #define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12) 452*4882a593Smuzhiyun #define GPIO_PAR_DT2IN_MASK (0x3000) 453*4882a593Smuzhiyun #define GPIO_PAR_DT2IN_DT2OUT (0x1000) 454*4882a593Smuzhiyun #define GPIO_PAR_DT2IN_DREQ2 (0x2000) 455*4882a593Smuzhiyun #define GPIO_PAR_DT2IN_DT2IN (0x3000) 456*4882a593Smuzhiyun #define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10) 457*4882a593Smuzhiyun #define GPIO_PAR_DT1IN_MASK (0x0C00) 458*4882a593Smuzhiyun #define GPIO_PAR_DT1IN_DT1OUT (0x0400) 459*4882a593Smuzhiyun #define GPIO_PAR_DT1IN_DREQ1 (0x0800) 460*4882a593Smuzhiyun #define GPIO_PAR_DT1IN_DT1IN (0x0C00) 461*4882a593Smuzhiyun #define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8) 462*4882a593Smuzhiyun #define GPIO_PAR_DT0IN_MASK (0x0300) 463*4882a593Smuzhiyun #define GPIO_PAR_DT0IN_DREQ0 (0x0200) 464*4882a593Smuzhiyun #define GPIO_PAR_DT0IN_DT0IN (0x0300) 465*4882a593Smuzhiyun #define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6) 466*4882a593Smuzhiyun #define GPIO_PAR_DT3OUT_MASK (0x00C0) 467*4882a593Smuzhiyun #define GPIO_PAR_DT3OUT_QSPICS3 (0x0040) 468*4882a593Smuzhiyun #define GPIO_PAR_DT3OUT_U2RTS (0x0080) 469*4882a593Smuzhiyun #define GPIO_PAR_DT3OUT_DT3OUT (0x00C0) 470*4882a593Smuzhiyun #define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4) 471*4882a593Smuzhiyun #define GPIO_PAR_DT2OUT_MASK (0x0030) 472*4882a593Smuzhiyun #define GPIO_PAR_DT2OUT_DACK2 (0x0020) 473*4882a593Smuzhiyun #define GPIO_PAR_DT2OUT_DT2OUT (0x0030) 474*4882a593Smuzhiyun #define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2) 475*4882a593Smuzhiyun #define GPIO_PAR_DT1OUT_MASK (0x000C) 476*4882a593Smuzhiyun #define GPIO_PAR_DT1OUT_DACK1 (0x0008) 477*4882a593Smuzhiyun #define GPIO_PAR_DT1OUT_DT1OUT (0x000C) 478*4882a593Smuzhiyun #define GPIO_PAR_DT0OUT(x) ((x)&0x03) 479*4882a593Smuzhiyun #define GPIO_PAR_DT0OUT_MASK (0x0003) 480*4882a593Smuzhiyun #define GPIO_PAR_DT0OUT_DACK0 (0x0002) 481*4882a593Smuzhiyun #define GPIO_PAR_DT0OUT_DT0OUT (0x0003) 482*4882a593Smuzhiyun #define GPIO_PAR_ETPU_TCRCLK (0x04) 483*4882a593Smuzhiyun #define GPIO_PAR_ETPU_UTPU_ODIS (0x02) 484*4882a593Smuzhiyun #define GPIO_PAR_ETPU_LTPU_ODIS (0x01) 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun /* Bit definitions and macros for GPIO_DSCR */ 487*4882a593Smuzhiyun #define GPIO_DSCR_EIM_EIM1 (0x10) 488*4882a593Smuzhiyun #define GPIO_DSCR_EIM_EIM0 (0x01) 489*4882a593Smuzhiyun #define GPIO_DSCR_ETPU_ETPU31_24 (0x40) 490*4882a593Smuzhiyun #define GPIO_DSCR_ETPU_ETPU23_16 (0x10) 491*4882a593Smuzhiyun #define GPIO_DSCR_ETPU_ETPU15_8 (0x04) 492*4882a593Smuzhiyun #define GPIO_DSCR_ETPU_ETPU7_0 (0x01) 493*4882a593Smuzhiyun #define GPIO_DSCR_FECI2C_FEC (0x10) 494*4882a593Smuzhiyun #define GPIO_DSCR_FECI2C_I2C (0x01) 495*4882a593Smuzhiyun #define GPIO_DSCR_UART_IRQ (0x40) 496*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART2 (0x10) 497*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART1 (0x04) 498*4882a593Smuzhiyun #define GPIO_DSCR_UART_UART0 (0x01) 499*4882a593Smuzhiyun #define GPIO_DSCR_QSPI_QSPI (0x01) 500*4882a593Smuzhiyun #define GPIO_DSCR_TIMER (0x01) 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun /********************************************************************* 503*4882a593Smuzhiyun * Chip Configuration Module (CCM) 504*4882a593Smuzhiyun *********************************************************************/ 505*4882a593Smuzhiyun /* Bit definitions and macros for CCM_RCR */ 506*4882a593Smuzhiyun #define CCM_RCR_SOFTRST (0x80) 507*4882a593Smuzhiyun #define CCM_RCR_FRCRSTOUT (0x40) 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun /* Bit definitions and macros for CCM_RSR */ 510*4882a593Smuzhiyun #define CCM_RSR_SOFT (0x20) 511*4882a593Smuzhiyun #define CCM_RSR_WDR (0x10) 512*4882a593Smuzhiyun #define CCM_RSR_POR (0x08) 513*4882a593Smuzhiyun #define CCM_RSR_EXT (0x04) 514*4882a593Smuzhiyun #define CCM_RSR_LOC (0x02) 515*4882a593Smuzhiyun #define CCM_RSR_LOL (0x01) 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun /* Bit definitions and macros for CCM_CCR */ 518*4882a593Smuzhiyun #define CCM_CCR_LOAD (0x8000) 519*4882a593Smuzhiyun #define CCM_CCR_SZEN (0x0040) 520*4882a593Smuzhiyun #define CCM_CCR_PSTEN (0x0020) 521*4882a593Smuzhiyun #define CCM_CCR_BME (0x0008) 522*4882a593Smuzhiyun #define CCM_CCR_BMT(x) ((x)&0x07) 523*4882a593Smuzhiyun #define CCM_CCR_BMT_MASK (0x0007) 524*4882a593Smuzhiyun #define CCM_CCR_BMT_64K (0x0000) 525*4882a593Smuzhiyun #define CCM_CCR_BMT_32K (0x0001) 526*4882a593Smuzhiyun #define CCM_CCR_BMT_16K (0x0002) 527*4882a593Smuzhiyun #define CCM_CCR_BMT_8K (0x0003) 528*4882a593Smuzhiyun #define CCM_CCR_BMT_4K (0x0004) 529*4882a593Smuzhiyun #define CCM_CCR_BMT_2K (0x0005) 530*4882a593Smuzhiyun #define CCM_CCR_BMT_1K (0x0006) 531*4882a593Smuzhiyun #define CCM_CCR_BMT_512 (0x0007) 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun /* Bit definitions and macros for CCM_RCON */ 534*4882a593Smuzhiyun #define CCM_RCON_RCSC(x) (((x)&0x0003)<<8) 535*4882a593Smuzhiyun #define CCM_RCON_RLOAD (0x0020) 536*4882a593Smuzhiyun #define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) 537*4882a593Smuzhiyun #define CCM_RCON_BOOTPS_MASK (0x0018) 538*4882a593Smuzhiyun #define CCM_RCON_BOOTPS_32 (0x0018) 539*4882a593Smuzhiyun #define CCM_RCON_BOOTPS_16 (0x0008) 540*4882a593Smuzhiyun #define CCM_RCON_BOOTPS_8 (0x0010) 541*4882a593Smuzhiyun #define CCM_RCON_MODE (0x0001) 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun /* Bit definitions and macros for CCM_CIR */ 544*4882a593Smuzhiyun #define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) 545*4882a593Smuzhiyun #define CCM_CIR_PRN(x) ((x) & 0x003F) 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun /********************************************************************* 548*4882a593Smuzhiyun * PLL Clock Module 549*4882a593Smuzhiyun *********************************************************************/ 550*4882a593Smuzhiyun /* Bit definitions and macros for PLL_SYNCR */ 551*4882a593Smuzhiyun #define PLL_SYNCR_MFD(x) (((x)&0x07)<<24) 552*4882a593Smuzhiyun #define PLL_SYNCR_MFD_MASK (0x07000000) 553*4882a593Smuzhiyun #define PLL_SYNCR_RFC(x) (((x)&0x07)<<19) 554*4882a593Smuzhiyun #define PLL_SYNCR_RFC_MASK (0x00380000) 555*4882a593Smuzhiyun #define PLL_SYNCR_LOCEN (0x00040000) 556*4882a593Smuzhiyun #define PLL_SYNCR_LOLRE (0x00020000) 557*4882a593Smuzhiyun #define PLL_SYNCR_LOCRE (0x00010000) 558*4882a593Smuzhiyun #define PLL_SYNCR_DISCLK (0x00008000) 559*4882a593Smuzhiyun #define PLL_SYNCR_LOLIRQ (0x00004000) 560*4882a593Smuzhiyun #define PLL_SYNCR_LOCIRQ (0x00002000) 561*4882a593Smuzhiyun #define PLL_SYNCR_RATE (0x00001000) 562*4882a593Smuzhiyun #define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10) 563*4882a593Smuzhiyun #define PLL_SYNCR_EXP(x) ((x)&0x03FF) 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun /* Bit definitions and macros for PLL_SYNSR */ 566*4882a593Smuzhiyun #define PLL_SYNSR_LOLF (0x00000200) 567*4882a593Smuzhiyun #define PLL_SYNSR_LOC (0x00000100) 568*4882a593Smuzhiyun #define PLL_SYNSR_MODE (0x00000080) 569*4882a593Smuzhiyun #define PLL_SYNSR_PLLSEL (0x00000040) 570*4882a593Smuzhiyun #define PLL_SYNSR_PLLREF (0x00000020) 571*4882a593Smuzhiyun #define PLL_SYNSR_LOCKS (0x00000010) 572*4882a593Smuzhiyun #define PLL_SYNSR_LOCK (0x00000008) 573*4882a593Smuzhiyun #define PLL_SYNSR_LOCF (0x00000004) 574*4882a593Smuzhiyun #define PLL_SYNSR_CALDONE (0x00000002) 575*4882a593Smuzhiyun #define PLL_SYNSR_CALPASS (0x00000001) 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun /********************************************************************* 578*4882a593Smuzhiyun * Watchdog Timer Modules (WTM) 579*4882a593Smuzhiyun *********************************************************************/ 580*4882a593Smuzhiyun /* Bit definitions and macros for WTM_WCR */ 581*4882a593Smuzhiyun #define WTM_WCR_WAIT (0x0008) 582*4882a593Smuzhiyun #define WTM_WCR_DOZE (0x0004) 583*4882a593Smuzhiyun #define WTM_WCR_HALTED (0x0002) 584*4882a593Smuzhiyun #define WTM_WCR_EN (0x0001) 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun #endif /* mcf5235_h */ 587