1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * ColdFire Internal Memory Map and Defines 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2004-2012 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __IMMAP_H 11*4882a593Smuzhiyun #define __IMMAP_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #if defined(CONFIG_MCF520x) 14*4882a593Smuzhiyun #include <asm/immap_520x.h> 15*4882a593Smuzhiyun #include <asm/m520x.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 18*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Timer */ 21*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 22*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 23*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 24*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 25*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 26*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 27*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 28*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (6) 29*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 30*4882a593Smuzhiyun #endif 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifdef CONFIG_MCFPIT 33*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 34*4882a593Smuzhiyun #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 35*4882a593Smuzhiyun #define CONFIG_SYS_PIT_PRESCALE (6) 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 39*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 40*4882a593Smuzhiyun #endif /* CONFIG_M520x */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #ifdef CONFIG_M52277 43*4882a593Smuzhiyun #include <asm/immap_5227x.h> 44*4882a593Smuzhiyun #include <asm/m5227x.h> 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #ifdef CONFIG_LCD 51*4882a593Smuzhiyun #define CONFIG_SYS_LCD_BASE (MMAP_LCD) 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Timer */ 55*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 56*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 57*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 58*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 59*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 60*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 61*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 62*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (6) 63*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 64*4882a593Smuzhiyun #endif 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #ifdef CONFIG_MCFPIT 67*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 68*4882a593Smuzhiyun #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 69*4882a593Smuzhiyun #define CONFIG_SYS_PIT_PRESCALE (6) 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 73*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 74*4882a593Smuzhiyun #endif /* CONFIG_M52277 */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #ifdef CONFIG_M5235 77*4882a593Smuzhiyun #include <asm/immap_5235.h> 78*4882a593Smuzhiyun #include <asm/m5235.h> 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 81*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* Timer */ 84*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 85*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 86*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 87*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 88*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 89*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 90*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 91*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ 92*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 93*4882a593Smuzhiyun #endif 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #ifdef CONFIG_MCFPIT 96*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 97*4882a593Smuzhiyun #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 98*4882a593Smuzhiyun #define CONFIG_SYS_PIT_PRESCALE (6) 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 102*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 103*4882a593Smuzhiyun #endif /* CONFIG_M5235 */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #ifdef CONFIG_M5249 106*4882a593Smuzhiyun #include <asm/immap_5249.h> 107*4882a593Smuzhiyun #include <asm/m5249.h> 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 112*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (64) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* Timer */ 115*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 116*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 117*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 118*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) 119*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (31) 120*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (0x00000400) 121*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 122*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) 123*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) 124*4882a593Smuzhiyun #endif 125*4882a593Smuzhiyun #endif /* CONFIG_M5249 */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #ifdef CONFIG_M5253 128*4882a593Smuzhiyun #include <asm/immap_5253.h> 129*4882a593Smuzhiyun #include <asm/m5249.h> 130*4882a593Smuzhiyun #include <asm/m5253.h> 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 135*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (64) 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* Timer */ 138*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 139*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 140*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 141*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) 142*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (27) 143*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (0x00000400) 144*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 145*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) 146*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) 147*4882a593Smuzhiyun #endif 148*4882a593Smuzhiyun #endif /* CONFIG_M5253 */ 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #ifdef CONFIG_M5271 151*4882a593Smuzhiyun #include <asm/immap_5271.h> 152*4882a593Smuzhiyun #include <asm/m5271.h> 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 155*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* Timer */ 158*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 159*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 160*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 161*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 162*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 163*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 164*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 165*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */ 166*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 167*4882a593Smuzhiyun #endif 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 170*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 171*4882a593Smuzhiyun #endif /* CONFIG_M5271 */ 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #ifdef CONFIG_M5272 174*4882a593Smuzhiyun #include <asm/immap_5272.h> 175*4882a593Smuzhiyun #include <asm/m5272.h> 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 178*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 181*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (64) 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* Timer */ 184*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 185*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0) 186*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_TMR3) 187*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr) 188*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT_TMR3) 189*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24) 190*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (0) 191*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) 192*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 193*4882a593Smuzhiyun #endif 194*4882a593Smuzhiyun #endif /* CONFIG_M5272 */ 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #ifdef CONFIG_M5275 197*4882a593Smuzhiyun #include <asm/immap_5275.h> 198*4882a593Smuzhiyun #include <asm/m5275.h> 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 201*4882a593Smuzhiyun #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 202*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 205*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (192) 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* Timer */ 208*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 209*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 210*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 211*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 212*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 213*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 214*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 215*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (0x1E) 216*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 217*4882a593Smuzhiyun #endif 218*4882a593Smuzhiyun #endif /* CONFIG_M5275 */ 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun #ifdef CONFIG_M5282 221*4882a593Smuzhiyun #include <asm/immap_5282.h> 222*4882a593Smuzhiyun #include <asm/m5282.h> 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 225*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 228*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun /* Timer */ 231*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 232*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 233*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 234*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 235*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 236*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3) 237*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 238*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ 239*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 240*4882a593Smuzhiyun #endif 241*4882a593Smuzhiyun #endif /* CONFIG_M5282 */ 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun #ifdef CONFIG_M5307 244*4882a593Smuzhiyun #include <asm/immap_5307.h> 245*4882a593Smuzhiyun #include <asm/m5307.h> 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ 248*4882a593Smuzhiyun (CONFIG_SYS_UART_PORT * 0x40)) 249*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 250*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (64) 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun /* Timer */ 253*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 254*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 255*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 256*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \ 257*4882a593Smuzhiyun (CONFIG_SYS_INTR_BASE))->ipr) 258*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (31) 259*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (0x00000400) 260*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 261*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \ 262*4882a593Smuzhiyun MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) 263*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 264*4882a593Smuzhiyun #endif 265*4882a593Smuzhiyun #endif /* CONFIG_M5307 */ 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun #if defined(CONFIG_MCF5301x) 268*4882a593Smuzhiyun #include <asm/immap_5301x.h> 269*4882a593Smuzhiyun #include <asm/m5301x.h> 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 272*4882a593Smuzhiyun #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 273*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun /* Timer */ 278*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 279*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 280*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 281*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 282*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 283*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 284*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 285*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (6) 286*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 287*4882a593Smuzhiyun #endif 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun #ifdef CONFIG_MCFPIT 290*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 291*4882a593Smuzhiyun #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 292*4882a593Smuzhiyun #define CONFIG_SYS_PIT_PRESCALE (6) 293*4882a593Smuzhiyun #endif 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 296*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 297*4882a593Smuzhiyun #endif /* CONFIG_M5301x */ 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun #if defined(CONFIG_M5329) || defined(CONFIG_M5373) 300*4882a593Smuzhiyun #include <asm/immap_5329.h> 301*4882a593Smuzhiyun #include <asm/m5329.h> 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 304*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 305*4882a593Smuzhiyun #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* Timer */ 308*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 309*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 310*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 311*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 312*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 313*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 314*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 315*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (6) 316*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 317*4882a593Smuzhiyun #endif 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun #ifdef CONFIG_MCFPIT 320*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 321*4882a593Smuzhiyun #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 322*4882a593Smuzhiyun #define CONFIG_SYS_PIT_PRESCALE (6) 323*4882a593Smuzhiyun #endif 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 326*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 327*4882a593Smuzhiyun #endif /* CONFIG_M5329 && CONFIG_M5373 */ 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun #if defined(CONFIG_M54418) 330*4882a593Smuzhiyun #include <asm/immap_5441x.h> 331*4882a593Smuzhiyun #include <asm/m5441x.h> 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 334*4882a593Smuzhiyun #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun #if (CONFIG_SYS_UART_PORT < 4) 337*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ 338*4882a593Smuzhiyun (CONFIG_SYS_UART_PORT * 0x4000)) 339*4882a593Smuzhiyun #else 340*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ 341*4882a593Smuzhiyun ((CONFIG_SYS_UART_PORT - 4) * 0x4000)) 342*4882a593Smuzhiyun #endif 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define MMAP_DSPI MMAP_DSPI0 345*4882a593Smuzhiyun #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun /* Timer */ 348*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 349*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 350*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 351*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 352*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 353*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 354*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 355*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (6) 356*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 357*4882a593Smuzhiyun #endif 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun #ifdef CONFIG_MCFPIT 360*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 361*4882a593Smuzhiyun #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 362*4882a593Smuzhiyun #define CONFIG_SYS_PIT_PRESCALE (6) 363*4882a593Smuzhiyun #endif 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 366*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun #endif /* CONFIG_M54418 */ 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun #if defined(CONFIG_M54451) || defined(CONFIG_M54455) 371*4882a593Smuzhiyun #include <asm/immap_5445x.h> 372*4882a593Smuzhiyun #include <asm/m5445x.h> 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 375*4882a593Smuzhiyun #if defined(CONFIG_M54455EVB) 376*4882a593Smuzhiyun #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 377*4882a593Smuzhiyun #endif 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun /* Timer */ 384*4882a593Smuzhiyun #ifdef CONFIG_MCFTMR 385*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 386*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 387*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 388*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 389*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 390*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 391*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (6) 392*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 393*4882a593Smuzhiyun #endif 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun #ifdef CONFIG_MCFPIT 396*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 397*4882a593Smuzhiyun #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 398*4882a593Smuzhiyun #define CONFIG_SYS_PIT_PRESCALE (6) 399*4882a593Smuzhiyun #endif 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 402*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun #ifdef CONFIG_PCI 405*4882a593Smuzhiyun #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) 406*4882a593Smuzhiyun #define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE) 407*4882a593Smuzhiyun #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 408*4882a593Smuzhiyun #define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE) 409*4882a593Smuzhiyun #endif 410*4882a593Smuzhiyun #endif /* CONFIG_M54451 || CONFIG_M54455 */ 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun #ifdef CONFIG_M547x 413*4882a593Smuzhiyun #include <asm/immap_547x_8x.h> 414*4882a593Smuzhiyun #include <asm/m547x_8x.h> 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun #ifdef CONFIG_FSLDMAFEC 417*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 418*4882a593Smuzhiyun #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun #define FEC0_RX_TASK 0 421*4882a593Smuzhiyun #define FEC0_TX_TASK 1 422*4882a593Smuzhiyun #define FEC0_RX_PRIORITY 6 423*4882a593Smuzhiyun #define FEC0_TX_PRIORITY 7 424*4882a593Smuzhiyun #define FEC0_RX_INIT 16 425*4882a593Smuzhiyun #define FEC0_TX_INIT 17 426*4882a593Smuzhiyun #define FEC1_RX_TASK 2 427*4882a593Smuzhiyun #define FEC1_TX_TASK 3 428*4882a593Smuzhiyun #define FEC1_RX_PRIORITY 6 429*4882a593Smuzhiyun #define FEC1_TX_PRIORITY 7 430*4882a593Smuzhiyun #define FEC1_RX_INIT 30 431*4882a593Smuzhiyun #define FEC1_TX_INIT 31 432*4882a593Smuzhiyun #endif 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun #ifdef CONFIG_SLTTMR 437*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) 438*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_SLT0) 439*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 440*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) 441*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) 442*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 443*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (0x1E) 444*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) 445*4882a593Smuzhiyun #endif 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 448*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun #ifdef CONFIG_PCI 451*4882a593Smuzhiyun #define CONFIG_SYS_PCI_BAR0 (0x40000000) 452*4882a593Smuzhiyun #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) 453*4882a593Smuzhiyun #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 454*4882a593Smuzhiyun #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) 455*4882a593Smuzhiyun #endif 456*4882a593Smuzhiyun #endif /* CONFIG_M547x */ 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun #ifdef CONFIG_M548x 459*4882a593Smuzhiyun #include <asm/immap_547x_8x.h> 460*4882a593Smuzhiyun #include <asm/m547x_8x.h> 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun #ifdef CONFIG_FSLDMAFEC 463*4882a593Smuzhiyun #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 464*4882a593Smuzhiyun #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun #define FEC0_RX_TASK 0 467*4882a593Smuzhiyun #define FEC0_TX_TASK 1 468*4882a593Smuzhiyun #define FEC0_RX_PRIORITY 6 469*4882a593Smuzhiyun #define FEC0_TX_PRIORITY 7 470*4882a593Smuzhiyun #define FEC0_RX_INIT 16 471*4882a593Smuzhiyun #define FEC0_TX_INIT 17 472*4882a593Smuzhiyun #define FEC1_RX_TASK 2 473*4882a593Smuzhiyun #define FEC1_TX_TASK 3 474*4882a593Smuzhiyun #define FEC1_RX_PRIORITY 6 475*4882a593Smuzhiyun #define FEC1_TX_PRIORITY 7 476*4882a593Smuzhiyun #define FEC1_RX_INIT 30 477*4882a593Smuzhiyun #define FEC1_TX_INIT 31 478*4882a593Smuzhiyun #endif 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun /* Timer */ 483*4882a593Smuzhiyun #ifdef CONFIG_SLTTMR 484*4882a593Smuzhiyun #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) 485*4882a593Smuzhiyun #define CONFIG_SYS_TMR_BASE (MMAP_SLT0) 486*4882a593Smuzhiyun #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 487*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) 488*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) 489*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 490*4882a593Smuzhiyun #define CONFIG_SYS_TMRINTR_PRI (0x1E) 491*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) 492*4882a593Smuzhiyun #endif 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 495*4882a593Smuzhiyun #define CONFIG_SYS_NUM_IRQS (128) 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun #ifdef CONFIG_PCI 498*4882a593Smuzhiyun #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) 499*4882a593Smuzhiyun #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) 500*4882a593Smuzhiyun #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 501*4882a593Smuzhiyun #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) 502*4882a593Smuzhiyun #endif 503*4882a593Smuzhiyun #endif /* CONFIG_M548x */ 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun #endif /* __IMMAP_H */ 506