1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Symmetric Key Hardware Accelerator Memory Map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __SKHA_H__ 11*4882a593Smuzhiyun #define __SKHA_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun typedef struct skha_ctrl { 14*4882a593Smuzhiyun u32 mr; /* 0x00 Mode */ 15*4882a593Smuzhiyun u32 cr; /* 0x04 Control */ 16*4882a593Smuzhiyun u32 cmr; /* 0x08 Command */ 17*4882a593Smuzhiyun u32 sr; /* 0x0C Status */ 18*4882a593Smuzhiyun u32 esr; /* 0x10 Error Status */ 19*4882a593Smuzhiyun u32 emr; /* 0x14 Error Status Mask Register) */ 20*4882a593Smuzhiyun u32 ksr; /* 0x18 Key Size */ 21*4882a593Smuzhiyun u32 dsr; /* 0x1C Data Size */ 22*4882a593Smuzhiyun u32 in; /* 0x20 Input FIFO */ 23*4882a593Smuzhiyun u32 out; /* 0x24 Output FIFO */ 24*4882a593Smuzhiyun u32 res1[2]; /* 0x28 - 0x2F */ 25*4882a593Smuzhiyun u32 kdr1; /* 0x30 Key Data 1 */ 26*4882a593Smuzhiyun u32 kdr2; /* 0x34 Key Data 2 */ 27*4882a593Smuzhiyun u32 kdr3; /* 0x38 Key Data 3 */ 28*4882a593Smuzhiyun u32 kdr4; /* 0x3C Key Data 4 */ 29*4882a593Smuzhiyun u32 kdr5; /* 0x40 Key Data 5 */ 30*4882a593Smuzhiyun u32 kdr6; /* 0x44 Key Data 6 */ 31*4882a593Smuzhiyun u32 res2[10]; /* 0x48 - 0x6F */ 32*4882a593Smuzhiyun u32 c1; /* 0x70 Context 1 */ 33*4882a593Smuzhiyun u32 c2; /* 0x74 Context 2 */ 34*4882a593Smuzhiyun u32 c3; /* 0x78 Context 3 */ 35*4882a593Smuzhiyun u32 c4; /* 0x7C Context 4 */ 36*4882a593Smuzhiyun u32 c5; /* 0x80 Context 5 */ 37*4882a593Smuzhiyun u32 c6; /* 0x84 Context 6 */ 38*4882a593Smuzhiyun u32 c7; /* 0x88 Context 7 */ 39*4882a593Smuzhiyun u32 c8; /* 0x8C Context 8 */ 40*4882a593Smuzhiyun u32 c9; /* 0x90 Context 9 */ 41*4882a593Smuzhiyun u32 c10; /* 0x94 Context 10 */ 42*4882a593Smuzhiyun u32 c11; /* 0x98 Context 11 */ 43*4882a593Smuzhiyun u32 c12; /* 0x9C Context 12 - 5235, 5271, 5272 */ 44*4882a593Smuzhiyun } skha_t; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #ifdef CONFIG_MCF532x 47*4882a593Smuzhiyun #define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 9) 48*4882a593Smuzhiyun #define SKHA_MODE_CTRM_MASK (0xFFFFE1FF) 49*4882a593Smuzhiyun #define SKHA_MODE_DKP (0x00000100) 50*4882a593Smuzhiyun #else 51*4882a593Smuzhiyun #define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 8) 52*4882a593Smuzhiyun #define SKHA_MODE_CTRM_MASK (0xFFFFF0FF) 53*4882a593Smuzhiyun #define SKHA_MODE_DKP (0x00000080) 54*4882a593Smuzhiyun #endif 55*4882a593Smuzhiyun #define SKHA_MODE_CM(x) (((x) & 0x03) << 3) 56*4882a593Smuzhiyun #define SKHA_MODE_CM_MASK (0xFFFFFFE7) 57*4882a593Smuzhiyun #define SKHA_MODE_DIR (0x00000004) 58*4882a593Smuzhiyun #define SKHA_MODE_ALG(x) ((x) & 0x03) 59*4882a593Smuzhiyun #define SKHA_MODE_ALG_MASK (0xFFFFFFFC) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define SHKA_CR_ODMAL(x) (((x) & 0x3F) << 24) 62*4882a593Smuzhiyun #define SHKA_CR_ODMAL_MASK (0xC0FFFFFF) 63*4882a593Smuzhiyun #define SHKA_CR_IDMAL(x) (((x) & 0x3F) << 16) 64*4882a593Smuzhiyun #define SHKA_CR_IDMAL_MASK (0xFFC0FFFF) 65*4882a593Smuzhiyun #define SHKA_CR_END (0x00000008) 66*4882a593Smuzhiyun #define SHKA_CR_ODMA (0x00000004) 67*4882a593Smuzhiyun #define SHKA_CR_IDMA (0x00000002) 68*4882a593Smuzhiyun #define SKHA_CR_IE (0x00000001) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define SKHA_CMR_GO (0x00000008) 71*4882a593Smuzhiyun #define SKHA_CMR_CI (0x00000004) 72*4882a593Smuzhiyun #define SKHA_CMR_RI (0x00000002) 73*4882a593Smuzhiyun #define SKHA_CMR_SWR (0x00000001) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define SKHA_SR_OFL(x) (((x) & 0xFF) << 24) 76*4882a593Smuzhiyun #define SKHA_SR_OFL_MASK (0x00FFFFFF) 77*4882a593Smuzhiyun #define SKHA_SR_IFL(x) (((x) & 0xFF) << 16) 78*4882a593Smuzhiyun #define SKHA_SR_IFL_MASK (0xFF00FFFF) 79*4882a593Smuzhiyun #define SKHA_SR_AESES(x) (((x) & 0x1F) << 11) 80*4882a593Smuzhiyun #define SKHA_SR_AESES_MASK (0xFFFF07FF) 81*4882a593Smuzhiyun #define SKHA_SR_DESES(x) (((x) & 0x7) << 8) 82*4882a593Smuzhiyun #define SKHA_SR_DESES_MASK (0xFFFFF8FF) 83*4882a593Smuzhiyun #define SKHA_SR_BUSY (0x00000010) 84*4882a593Smuzhiyun #define SKHA_SR_RD (0x00000008) 85*4882a593Smuzhiyun #define SKHA_SR_ERR (0x00000004) 86*4882a593Smuzhiyun #define SKHA_SR_DONE (0x00000002) 87*4882a593Smuzhiyun #define SKHA_SR_INT (0x00000001) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define SHKA_ESE_DRL (0x00000800) 90*4882a593Smuzhiyun #define SKHA_ESR_KRE (0x00000400) 91*4882a593Smuzhiyun #define SKHA_ESR_KPE (0x00000200) 92*4882a593Smuzhiyun #define SKHA_ESR_ERE (0x00000100) 93*4882a593Smuzhiyun #define SKHA_ESR_RMDP (0x00000080) 94*4882a593Smuzhiyun #define SKHA_ESR_KSE (0x00000040) 95*4882a593Smuzhiyun #define SKHA_ESR_DSE (0x00000020) 96*4882a593Smuzhiyun #define SKHA_ESR_IME (0x00000010) 97*4882a593Smuzhiyun #define SKHA_ESR_NEOF (0x00000008) 98*4882a593Smuzhiyun #define SKHA_ESR_NEIF (0x00000004) 99*4882a593Smuzhiyun #define SKHA_ESR_OFU (0x00000002) 100*4882a593Smuzhiyun #define SKHA_ESR_IFO (0x00000001) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define SKHA_KSR_SZ(x) ((x) & 0x3F) 103*4882a593Smuzhiyun #define SKHA_KSR_SZ_MASK (0xFFFFFFC0) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #endif /* __SKHA_H__ */ 106