1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * RNG Memory Map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __RNG_H__ 11*4882a593Smuzhiyun #define __RNG_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Random Number Generator */ 14*4882a593Smuzhiyun typedef struct rng_ctrl { 15*4882a593Smuzhiyun u32 cr; /* 0x00 Control */ 16*4882a593Smuzhiyun u32 sr; /* 0x04 Status */ 17*4882a593Smuzhiyun u32 er; /* 0x08 Entropy */ 18*4882a593Smuzhiyun u32 out; /* 0x0C Output FIFO */ 19*4882a593Smuzhiyun } rng_t; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define RNG_CR_SLM (0x00000010) /* Sleep mode - 5445x */ 22*4882a593Smuzhiyun #define RNG_CR_CI (0x00000008) /* Clear interrupt */ 23*4882a593Smuzhiyun #define RNG_CR_IM (0x00000004) /* Interrupt mask */ 24*4882a593Smuzhiyun #define RNG_CR_HA (0x00000002) /* High assurance */ 25*4882a593Smuzhiyun #define RNG_CR_GO (0x00000001) /* Go bit */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define RNG_SR_OFS(x) (((x) & 0x000000FF) << 16) 28*4882a593Smuzhiyun #define RNG_SR_OFS_MASK (0xFF00FFFF) 29*4882a593Smuzhiyun #define RNG_SR_OFL(x) (((x) & 0x000000FF) << 8) 30*4882a593Smuzhiyun #define RNG_SR_OFL_MASK (0xFFFF00FF) 31*4882a593Smuzhiyun #define RNG_SR_EI (0x00000008) 32*4882a593Smuzhiyun #define RNG_SR_FUF (0x00000004) 33*4882a593Smuzhiyun #define RNG_SR_LRS (0x00000002) 34*4882a593Smuzhiyun #define RNG_SR_SV (0x00000001) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __RNG_H__ */ 37