1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Pulse Width Modulation Memory Map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ATA_H__ 11*4882a593Smuzhiyun #define __ATA_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Pulse Width Modulation (PWM) */ 14*4882a593Smuzhiyun typedef struct pwm_ctrl { 15*4882a593Smuzhiyun #ifdef CONFIG_M5272 16*4882a593Smuzhiyun u8 cr0; 17*4882a593Smuzhiyun u8 res1[3]; 18*4882a593Smuzhiyun u8 cr1; 19*4882a593Smuzhiyun u8 res2[3]; 20*4882a593Smuzhiyun u8 cr2; 21*4882a593Smuzhiyun u8 res3[7]; 22*4882a593Smuzhiyun u8 pwr0; 23*4882a593Smuzhiyun u8 res4[3]; 24*4882a593Smuzhiyun u8 pwr1; 25*4882a593Smuzhiyun u8 res5[3]; 26*4882a593Smuzhiyun u8 pwr2; 27*4882a593Smuzhiyun u8 res6[7]; 28*4882a593Smuzhiyun #else 29*4882a593Smuzhiyun u8 en; /* 0x00 PWM Enable */ 30*4882a593Smuzhiyun u8 pol; /* 0x01 Polarity */ 31*4882a593Smuzhiyun u8 clk; /* 0x02 Clock Select */ 32*4882a593Smuzhiyun u8 prclk; /* 0x03 Prescale Clock Select */ 33*4882a593Smuzhiyun u8 cae; /* 0x04 Center Align Enable */ 34*4882a593Smuzhiyun u8 ctl; /* 0x05 Control */ 35*4882a593Smuzhiyun u16 res1; /* 0x06 - 0x07 */ 36*4882a593Smuzhiyun u8 scla; /* 0x08 Scale A */ 37*4882a593Smuzhiyun u8 sclb; /* 0x09 Scale B */ 38*4882a593Smuzhiyun u16 res2; /* 0x0A - 0x0B */ 39*4882a593Smuzhiyun #ifdef CONFIG_M5275 40*4882a593Smuzhiyun u8 cnt[4]; /* 0x0C Channel n Counter */ 41*4882a593Smuzhiyun u16 res3; /* 0x10 - 0x11 */ 42*4882a593Smuzhiyun u8 per[4]; /* 0x14 Channel n Period */ 43*4882a593Smuzhiyun u16 res4; /* 0x16 - 0x17 */ 44*4882a593Smuzhiyun u8 dty[4]; /* 0x18 Channel n Duty */ 45*4882a593Smuzhiyun #else 46*4882a593Smuzhiyun u8 cnt[8]; /* 0x0C Channel n Counter */ 47*4882a593Smuzhiyun u8 per[8]; /* 0x14 Channel n Period */ 48*4882a593Smuzhiyun u8 dty[8]; /* 0x1C Channel n Duty */ 49*4882a593Smuzhiyun u8 sdn; /* 0x24 Shutdown */ 50*4882a593Smuzhiyun u8 res3[3]; /* 0x25 - 0x27 */ 51*4882a593Smuzhiyun #endif /* CONFIG_M5275 */ 52*4882a593Smuzhiyun #endif /* CONFIG_M5272 */ 53*4882a593Smuzhiyun } pwm_t; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #ifdef CONFIG_M5272 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define PWM_CR_EN (0x80) 58*4882a593Smuzhiyun #define PWM_CR_FRC1 (0x40) 59*4882a593Smuzhiyun #define PWM_CR_LVL (0x20) 60*4882a593Smuzhiyun #define PWM_CR_CLKSEL(x) ((x) & 0x0F) 61*4882a593Smuzhiyun #define PWM_CR_CLKSEL_MASK (0xF0) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #else 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define PWM_EN_PWMEn(x) (1 << ((x) & 0x07)) 66*4882a593Smuzhiyun #define PWM_EN_PWMEn_MASK (0xF0) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define PWM_POL_PPOLn(x) (1 << ((x) & 0x07)) 69*4882a593Smuzhiyun #define PWM_POL_PPOLn_MASK (0xF0) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07)) 72*4882a593Smuzhiyun #define PWM_CLK_PCLKn_MASK (0xF0) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4) 75*4882a593Smuzhiyun #define PWM_PRCLK_PCKB_MASK (0x8F) 76*4882a593Smuzhiyun #define PWM_PRCLK_PCKA(x) ((x) & 0x07) 77*4882a593Smuzhiyun #define PWM_PRCLK_PCKA_MASK (0xF8) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07)) 80*4882a593Smuzhiyun #define PWM_CLK_PCLKn_MASK (0xF0) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define PWM_CTL_CON67 (0x80) 83*4882a593Smuzhiyun #define PWM_CTL_CON45 (0x40) 84*4882a593Smuzhiyun #define PWM_CTL_CON23 (0x20) 85*4882a593Smuzhiyun #define PWM_CTL_CON01 (0x10) 86*4882a593Smuzhiyun #define PWM_CTL_PSWAR (0x08) 87*4882a593Smuzhiyun #define PWM_CTL_PFRZ (0x04) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define PWM_SDN_IF (0x80) 90*4882a593Smuzhiyun #define PWM_SDN_IE (0x40) 91*4882a593Smuzhiyun #define PWM_SDN_RESTART (0x20) 92*4882a593Smuzhiyun #define PWM_SDN_LVL (0x10) 93*4882a593Smuzhiyun #define PWM_SDN_PWM7IN (0x04) 94*4882a593Smuzhiyun #define PWM_SDN_PWM7IL (0x02) 95*4882a593Smuzhiyun #define PWM_SDN_SDNEN (0x01) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif /* CONFIG_M5272 */ 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif /* __ATA_H__ */ 100