1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Message Digest Hardware Accelerator Memory Map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MDHA_H__ 11*4882a593Smuzhiyun #define __MDHA_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Message Digest Hardware Accelerator */ 14*4882a593Smuzhiyun typedef struct mdha_ctrl { 15*4882a593Smuzhiyun u32 mr; /* 0x00 MDHA Mode */ 16*4882a593Smuzhiyun u32 cr; /* 0x04 Control */ 17*4882a593Smuzhiyun u32 cmd; /* 0x08 Command */ 18*4882a593Smuzhiyun u32 sr; /* 0x0C Status */ 19*4882a593Smuzhiyun u32 isr; /* 0x10 Interrupt Status */ 20*4882a593Smuzhiyun u32 imr; /* 0x14 Interrupt Mask */ 21*4882a593Smuzhiyun u32 dsz; /* 0x1C Data Size */ 22*4882a593Smuzhiyun u32 inp; /* 0x20 Input FIFO */ 23*4882a593Smuzhiyun u32 res1[3]; /* 0x24 - 0x2F */ 24*4882a593Smuzhiyun u32 mda0; /* 0x30 Message Digest AO */ 25*4882a593Smuzhiyun u32 mdb0; /* 0x34 Message Digest BO */ 26*4882a593Smuzhiyun u32 mdc0; /* 0x38 Message Digest CO */ 27*4882a593Smuzhiyun u32 mdd0; /* 0x3C Message Digest DO */ 28*4882a593Smuzhiyun u32 mde0; /* 0x40 Message Digest EO */ 29*4882a593Smuzhiyun u32 mdsz; /* 0x44 Message Data Size */ 30*4882a593Smuzhiyun u32 res[10]; /* 0x48 - 0x6F */ 31*4882a593Smuzhiyun u32 mda1; /* 0x70 Message Digest A1 */ 32*4882a593Smuzhiyun u32 mdb1; /* 0x74 Message Digest B1 */ 33*4882a593Smuzhiyun u32 mdc1; /* 0x78 Message Digest C1 */ 34*4882a593Smuzhiyun u32 mdd1; /* 0x7C Message Digest D1 */ 35*4882a593Smuzhiyun u32 mde1; /* 0x80 Message Digest E1 */ 36*4882a593Smuzhiyun } mdha_t; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define MDHA_MR_SSL (0x00000400) 39*4882a593Smuzhiyun #define MDHA_MR_MACFUL (0x00000200) 40*4882a593Smuzhiyun #define MDHA_MR_SWAP (0x00000100) 41*4882a593Smuzhiyun #define MDHA_MR_OPAD (0x00000080) 42*4882a593Smuzhiyun #define MDHA_MR_IPAD (0x00000040) 43*4882a593Smuzhiyun #define MDHA_MR_INIT (0x00000020) 44*4882a593Smuzhiyun #define MDHA_MR_MAC(x) (((x) & 0x03) << 3) 45*4882a593Smuzhiyun #define MDHA_MR_MAC_MASK (0xFFFFFFE7) 46*4882a593Smuzhiyun #define MDHA_MR_MAC_EHMAC (0x00000010) 47*4882a593Smuzhiyun #define MDHA_MR_MAC_HMAC (0x00000008) 48*4882a593Smuzhiyun #define MDHA_MR_MAC_NONE (0x00000000) 49*4882a593Smuzhiyun #define MDHA_MR_PDATA (0x00000004) 50*4882a593Smuzhiyun #define MDHA_MR_ALG (0x00000001) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MDHA_CR_DMAL(x) (((x) & 0x1F) << 16) /* 532x */ 53*4882a593Smuzhiyun #define MDHA_CR_DMAL_MASK (0xFFE0FFFF) /* 532x */ 54*4882a593Smuzhiyun #define MDHA_CR_END (0x00000004) /* 532x */ 55*4882a593Smuzhiyun #define MDHA_CR_DMA (0x00000002) /* 532x */ 56*4882a593Smuzhiyun #define MDHA_CR_IE (0x00000001) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define MDHA_CMD_GO (0x00000008) 59*4882a593Smuzhiyun #define MDHA_CMD_CI (0x00000004) 60*4882a593Smuzhiyun #define MDHA_CMD_RI (0x00000001) 61*4882a593Smuzhiyun #define MDHA_CMD_SWR (0x00000001) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define MDHA_SR_IFL(x) (((x) & 0xFF) << 16) 64*4882a593Smuzhiyun #define MDHA_SR_IFL_MASK (0xFF00FFFF) 65*4882a593Smuzhiyun #define MDHA_SR_APD(x) (((x) & 0x7) << 13) 66*4882a593Smuzhiyun #define MDHA_SR_APD_MASK (0xFFFF1FFF) 67*4882a593Smuzhiyun #define MDHA_SR_FS(x) (((x) & 0x7) << 8) 68*4882a593Smuzhiyun #define MDHA_SR_FS_MASK (0xFFFFF8FF) 69*4882a593Smuzhiyun #define MDHA_SR_GNW (0x00000080) 70*4882a593Smuzhiyun #define MDHA_SR_HSH (0x00000040) 71*4882a593Smuzhiyun #define MDHA_SR_BUSY (0x00000010) 72*4882a593Smuzhiyun #define MDHA_SR_RD (0x00000008) 73*4882a593Smuzhiyun #define MDHA_SR_ERR (0x00000004) 74*4882a593Smuzhiyun #define MDHA_SR_DONE (0x00000002) 75*4882a593Smuzhiyun #define MDHA_SR_INT (0x00000001) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define MDHA_ISR_DRL (0x00000400) /* 532x */ 78*4882a593Smuzhiyun #define MDHA_ISR_GTDS (0x00000200) 79*4882a593Smuzhiyun #define MDHA_ISR_ERE (0x00000100) 80*4882a593Smuzhiyun #define MDHA_ISR_RMDP (0x00000080) 81*4882a593Smuzhiyun #define MDHA_ISR_DSE (0x00000020) 82*4882a593Smuzhiyun #define MDHA_ISR_IME (0x00000010) 83*4882a593Smuzhiyun #define MDHA_ISR_NEIF (0x00000004) 84*4882a593Smuzhiyun #define MDHA_ISR_IFO (0x00000001) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* __MDHA_H__ */ 87