1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * FlexBus Internal Memory Map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __FLEXBUS_H 11*4882a593Smuzhiyun #define __FLEXBUS_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /********************************************************************* 14*4882a593Smuzhiyun * FlexBus Chip Selects (FBCS) 15*4882a593Smuzhiyun *********************************************************************/ 16*4882a593Smuzhiyun #ifdef CONFIG_M5235 17*4882a593Smuzhiyun typedef struct fbcs { 18*4882a593Smuzhiyun u16 csar0; /* Chip-select Address */ 19*4882a593Smuzhiyun u16 res1; 20*4882a593Smuzhiyun u32 csmr0; /* Chip-select Mask */ 21*4882a593Smuzhiyun u16 res2; 22*4882a593Smuzhiyun u16 cscr0; /* Chip-select Control */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun u16 csar1; 25*4882a593Smuzhiyun u16 res3; 26*4882a593Smuzhiyun u32 csmr1; 27*4882a593Smuzhiyun u16 res4; 28*4882a593Smuzhiyun u16 cscr1; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun u16 csar2; 31*4882a593Smuzhiyun u16 res5; 32*4882a593Smuzhiyun u32 csmr2; 33*4882a593Smuzhiyun u16 res6; 34*4882a593Smuzhiyun u16 cscr2; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun u16 csar3; 37*4882a593Smuzhiyun u16 res7; 38*4882a593Smuzhiyun u32 csmr3; 39*4882a593Smuzhiyun u16 res8; 40*4882a593Smuzhiyun u16 cscr3; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun u16 csar4; 43*4882a593Smuzhiyun u16 res9; 44*4882a593Smuzhiyun u32 csmr4; 45*4882a593Smuzhiyun u16 res10; 46*4882a593Smuzhiyun u16 cscr4; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun u16 csar5; 49*4882a593Smuzhiyun u16 res11; 50*4882a593Smuzhiyun u32 csmr5; 51*4882a593Smuzhiyun u16 res12; 52*4882a593Smuzhiyun u16 cscr5; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun u16 csar6; 55*4882a593Smuzhiyun u16 res13; 56*4882a593Smuzhiyun u32 csmr6; 57*4882a593Smuzhiyun u16 res14; 58*4882a593Smuzhiyun u16 cscr6; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun u16 csar7; 61*4882a593Smuzhiyun u16 res15; 62*4882a593Smuzhiyun u32 csmr7; 63*4882a593Smuzhiyun u16 res16; 64*4882a593Smuzhiyun u16 cscr7; 65*4882a593Smuzhiyun } fbcs_t; 66*4882a593Smuzhiyun #else 67*4882a593Smuzhiyun typedef struct fbcs { 68*4882a593Smuzhiyun u32 csar0; /* Chip-select Address */ 69*4882a593Smuzhiyun u32 csmr0; /* Chip-select Mask */ 70*4882a593Smuzhiyun u32 cscr0; /* Chip-select Control */ 71*4882a593Smuzhiyun u32 csar1; 72*4882a593Smuzhiyun u32 csmr1; 73*4882a593Smuzhiyun u32 cscr1; 74*4882a593Smuzhiyun u32 csar2; 75*4882a593Smuzhiyun u32 csmr2; 76*4882a593Smuzhiyun u32 cscr2; 77*4882a593Smuzhiyun u32 csar3; 78*4882a593Smuzhiyun u32 csmr3; 79*4882a593Smuzhiyun u32 cscr3; 80*4882a593Smuzhiyun u32 csar4; 81*4882a593Smuzhiyun u32 csmr4; 82*4882a593Smuzhiyun u32 cscr4; 83*4882a593Smuzhiyun u32 csar5; 84*4882a593Smuzhiyun u32 csmr5; 85*4882a593Smuzhiyun u32 cscr5; 86*4882a593Smuzhiyun u32 csar6; 87*4882a593Smuzhiyun u32 csmr6; 88*4882a593Smuzhiyun u32 cscr6; 89*4882a593Smuzhiyun u32 csar7; 90*4882a593Smuzhiyun u32 csmr7; 91*4882a593Smuzhiyun u32 cscr7; 92*4882a593Smuzhiyun } fbcs_t; 93*4882a593Smuzhiyun #endif 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16) 98*4882a593Smuzhiyun #define FBCS_CSMR_BAM_MASK (0x0000FFFF) 99*4882a593Smuzhiyun #define FBCS_CSMR_BAM_4G (0xFFFF0000) 100*4882a593Smuzhiyun #define FBCS_CSMR_BAM_2G (0x7FFF0000) 101*4882a593Smuzhiyun #define FBCS_CSMR_BAM_1G (0x3FFF0000) 102*4882a593Smuzhiyun #define FBCS_CSMR_BAM_1024M (0x3FFF0000) 103*4882a593Smuzhiyun #define FBCS_CSMR_BAM_512M (0x1FFF0000) 104*4882a593Smuzhiyun #define FBCS_CSMR_BAM_256M (0x0FFF0000) 105*4882a593Smuzhiyun #define FBCS_CSMR_BAM_128M (0x07FF0000) 106*4882a593Smuzhiyun #define FBCS_CSMR_BAM_64M (0x03FF0000) 107*4882a593Smuzhiyun #define FBCS_CSMR_BAM_32M (0x01FF0000) 108*4882a593Smuzhiyun #define FBCS_CSMR_BAM_16M (0x00FF0000) 109*4882a593Smuzhiyun #define FBCS_CSMR_BAM_8M (0x007F0000) 110*4882a593Smuzhiyun #define FBCS_CSMR_BAM_4M (0x003F0000) 111*4882a593Smuzhiyun #define FBCS_CSMR_BAM_2M (0x001F0000) 112*4882a593Smuzhiyun #define FBCS_CSMR_BAM_1M (0x000F0000) 113*4882a593Smuzhiyun #define FBCS_CSMR_BAM_1024K (0x000F0000) 114*4882a593Smuzhiyun #define FBCS_CSMR_BAM_512K (0x00070000) 115*4882a593Smuzhiyun #define FBCS_CSMR_BAM_256K (0x00030000) 116*4882a593Smuzhiyun #define FBCS_CSMR_BAM_128K (0x00010000) 117*4882a593Smuzhiyun #define FBCS_CSMR_BAM_64K (0x00000000) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #ifdef CONFIG_M5249 120*4882a593Smuzhiyun #define FBCS_CSMR_WP (0x00000080) 121*4882a593Smuzhiyun #define FBCS_CSMR_AM (0x00000040) 122*4882a593Smuzhiyun #define FBCS_CSMR_CI (0x00000020) 123*4882a593Smuzhiyun #define FBCS_CSMR_SC (0x00000010) 124*4882a593Smuzhiyun #define FBCS_CSMR_SD (0x00000008) 125*4882a593Smuzhiyun #define FBCS_CSMR_UC (0x00000004) 126*4882a593Smuzhiyun #define FBCS_CSMR_UD (0x00000002) 127*4882a593Smuzhiyun #else 128*4882a593Smuzhiyun #define FBCS_CSMR_WP (0x00000100) 129*4882a593Smuzhiyun #endif 130*4882a593Smuzhiyun #define FBCS_CSMR_V (0x00000001) /* Valid bit */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #ifdef CONFIG_M5235 133*4882a593Smuzhiyun #define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14) 134*4882a593Smuzhiyun #define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10) 135*4882a593Smuzhiyun #define FBCS_CSCR_AA_ON (1 << 8) 136*4882a593Smuzhiyun #define FBCS_CSCR_AA_OFF (0 << 8) 137*4882a593Smuzhiyun #define FBCS_CSCR_PS_32 (0 << 6) 138*4882a593Smuzhiyun #define FBCS_CSCR_PS_16 (2 << 6) 139*4882a593Smuzhiyun #define FBCS_CSCR_PS_8 (1 << 6) 140*4882a593Smuzhiyun #define FBCS_CSCR_BEM_ON (1 << 5) 141*4882a593Smuzhiyun #define FBCS_CSCR_BEM_OFF (0 << 5) 142*4882a593Smuzhiyun #define FBCS_CSCR_BSTR_ON (1 << 4) 143*4882a593Smuzhiyun #define FBCS_CSCR_BSTR_OFF (0 << 4) 144*4882a593Smuzhiyun #define FBCS_CSCR_BSTW_ON (1 << 3) 145*4882a593Smuzhiyun #define FBCS_CSCR_BSTW_OFF (0 << 3) 146*4882a593Smuzhiyun #define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0) 147*4882a593Smuzhiyun #else 148*4882a593Smuzhiyun #define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26) 149*4882a593Smuzhiyun #define FBCS_CSCR_SWS_MASK (0x03FFFFFF) 150*4882a593Smuzhiyun #define FBCS_CSCR_SWSEN (0x00800000) 151*4882a593Smuzhiyun #define FBCS_CSCR_ASET(x) (((x) & 0x03) << 20) 152*4882a593Smuzhiyun #define FBCS_CSCR_ASET_MASK (0xFFCFFFFF) 153*4882a593Smuzhiyun #define FBCS_CSCR_RDAH(x) (((x) & 0x03) << 18) 154*4882a593Smuzhiyun #define FBCS_CSCR_RDAH_MASK (0xFFF3FFFF) 155*4882a593Smuzhiyun #define FBCS_CSCR_WRAH(x) (((x) & 0x03) << 16) 156*4882a593Smuzhiyun #define FBCS_CSCR_WRAH_MASK (0xFFFCFFFF) 157*4882a593Smuzhiyun #define FBCS_CSCR_WS(x) (((x) & 0x3F) << 10) 158*4882a593Smuzhiyun #define FBCS_CSCR_WS_MASK (0xFFFF03FF) 159*4882a593Smuzhiyun #define FBCS_CSCR_SBM (0x00000200) 160*4882a593Smuzhiyun #define FBCS_CSCR_AA (0x00000100) 161*4882a593Smuzhiyun #define FBCS_CSCR_PS(x) (((x) & 0x03) << 6) 162*4882a593Smuzhiyun #define FBCS_CSCR_PS_MASK (0xFFFFFF3F) 163*4882a593Smuzhiyun #define FBCS_CSCR_BEM (0x00000020) 164*4882a593Smuzhiyun #define FBCS_CSCR_BSTR (0x00000010) 165*4882a593Smuzhiyun #define FBCS_CSCR_BSTW (0x00000008) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define FBCS_CSCR_PS_16 (0x00000080) 168*4882a593Smuzhiyun #define FBCS_CSCR_PS_8 (0x00000040) 169*4882a593Smuzhiyun #define FBCS_CSCR_PS_32 (0x00000000) 170*4882a593Smuzhiyun #endif 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #endif /* __FLEXBUS_H */ 173