1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Edge Port Memory Map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __EPORT_H__ 11*4882a593Smuzhiyun #define __EPORT_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Edge Port Module (EPORT) */ 14*4882a593Smuzhiyun typedef struct eport { 15*4882a593Smuzhiyun #ifdef CONFIG_MCF547x_8x 16*4882a593Smuzhiyun u16 par; /* 0x00 */ 17*4882a593Smuzhiyun u16 res0; /* 0x02 */ 18*4882a593Smuzhiyun u8 ddr; /* 0x04 */ 19*4882a593Smuzhiyun u8 ier; /* 0x05 */ 20*4882a593Smuzhiyun u16 res1; /* 0x06 */ 21*4882a593Smuzhiyun u8 dr; /* 0x08 */ 22*4882a593Smuzhiyun u8 pdr; /* 0x09 */ 23*4882a593Smuzhiyun u16 res2; /* 0x0A */ 24*4882a593Smuzhiyun u8 fr; /* 0x0C */ 25*4882a593Smuzhiyun u8 res3[3]; /* 0x0D */ 26*4882a593Smuzhiyun #else 27*4882a593Smuzhiyun u16 par; /* 0x00 Pin Assignment */ 28*4882a593Smuzhiyun u8 ddr; /* 0x02 Data Direction */ 29*4882a593Smuzhiyun u8 ier; /* 0x03 Interrupt Enable */ 30*4882a593Smuzhiyun u8 dr; /* 0x04 Data */ 31*4882a593Smuzhiyun u8 pdr; /* 0x05 Pin Data */ 32*4882a593Smuzhiyun u8 fr; /* 0x06 Flag */ 33*4882a593Smuzhiyun u8 res0; 34*4882a593Smuzhiyun #endif 35*4882a593Smuzhiyun } eport_t; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* EPPAR */ 38*4882a593Smuzhiyun #define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2) 39*4882a593Smuzhiyun #define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4) 40*4882a593Smuzhiyun #define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6) 41*4882a593Smuzhiyun #define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8) 42*4882a593Smuzhiyun #define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10) 43*4882a593Smuzhiyun #define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12) 44*4882a593Smuzhiyun #define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14) 45*4882a593Smuzhiyun #define EPORT_PAR_LEVEL (0) 46*4882a593Smuzhiyun #define EPORT_PAR_RISING (1) 47*4882a593Smuzhiyun #define EPORT_PAR_FALLING (2) 48*4882a593Smuzhiyun #define EPORT_PAR_BOTH (3) 49*4882a593Smuzhiyun #define EPORT_PAR_EPPA7_LEVEL (0x0000) 50*4882a593Smuzhiyun #define EPORT_PAR_EPPA7_RISING (0x4000) 51*4882a593Smuzhiyun #define EPORT_PAR_EPPA7_FALLING (0x8000) 52*4882a593Smuzhiyun #define EPORT_PAR_EPPA7_BOTH (0xC000) 53*4882a593Smuzhiyun #define EPORT_PAR_EPPA6_LEVEL (0x0000) 54*4882a593Smuzhiyun #define EPORT_PAR_EPPA6_RISING (0x1000) 55*4882a593Smuzhiyun #define EPORT_PAR_EPPA6_FALLING (0x2000) 56*4882a593Smuzhiyun #define EPORT_PAR_EPPA6_BOTH (0x3000) 57*4882a593Smuzhiyun #define EPORT_PAR_EPPA5_LEVEL (0x0000) 58*4882a593Smuzhiyun #define EPORT_PAR_EPPA5_RISING (0x0400) 59*4882a593Smuzhiyun #define EPORT_PAR_EPPA5_FALLING (0x0800) 60*4882a593Smuzhiyun #define EPORT_PAR_EPPA5_BOTH (0x0C00) 61*4882a593Smuzhiyun #define EPORT_PAR_EPPA4_LEVEL (0x0000) 62*4882a593Smuzhiyun #define EPORT_PAR_EPPA4_RISING (0x0100) 63*4882a593Smuzhiyun #define EPORT_PAR_EPPA4_FALLING (0x0200) 64*4882a593Smuzhiyun #define EPORT_PAR_EPPA4_BOTH (0x0300) 65*4882a593Smuzhiyun #define EPORT_PAR_EPPA3_LEVEL (0x0000) 66*4882a593Smuzhiyun #define EPORT_PAR_EPPA3_RISING (0x0040) 67*4882a593Smuzhiyun #define EPORT_PAR_EPPA3_FALLING (0x0080) 68*4882a593Smuzhiyun #define EPORT_PAR_EPPA3_BOTH (0x00C0) 69*4882a593Smuzhiyun #define EPORT_PAR_EPPA2_LEVEL (0x0000) 70*4882a593Smuzhiyun #define EPORT_PAR_EPPA2_RISING (0x0010) 71*4882a593Smuzhiyun #define EPORT_PAR_EPPA2_FALLING (0x0020) 72*4882a593Smuzhiyun #define EPORT_PAR_EPPA2_BOTH (0x0030) 73*4882a593Smuzhiyun #define EPORT_PAR_EPPA1_LEVEL (0x0000) 74*4882a593Smuzhiyun #define EPORT_PAR_EPPA1_RISING (0x0004) 75*4882a593Smuzhiyun #define EPORT_PAR_EPPA1_FALLING (0x0008) 76*4882a593Smuzhiyun #define EPORT_PAR_EPPA1_BOTH (0x000C) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* EPDDR */ 79*4882a593Smuzhiyun #define EPORT_DDR_EPDD1 (0x02) 80*4882a593Smuzhiyun #define EPORT_DDR_EPDD2 (0x04) 81*4882a593Smuzhiyun #define EPORT_DDR_EPDD3 (0x08) 82*4882a593Smuzhiyun #define EPORT_DDR_EPDD4 (0x10) 83*4882a593Smuzhiyun #define EPORT_DDR_EPDD5 (0x20) 84*4882a593Smuzhiyun #define EPORT_DDR_EPDD6 (0x40) 85*4882a593Smuzhiyun #define EPORT_DDR_EPDD7 (0x80) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* EPIER */ 88*4882a593Smuzhiyun #define EPORT_IER_EPIE1 (0x02) 89*4882a593Smuzhiyun #define EPORT_IER_EPIE2 (0x04) 90*4882a593Smuzhiyun #define EPORT_IER_EPIE3 (0x08) 91*4882a593Smuzhiyun #define EPORT_IER_EPIE4 (0x10) 92*4882a593Smuzhiyun #define EPORT_IER_EPIE5 (0x20) 93*4882a593Smuzhiyun #define EPORT_IER_EPIE6 (0x40) 94*4882a593Smuzhiyun #define EPORT_IER_EPIE7 (0x80) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* EPDR */ 97*4882a593Smuzhiyun #define EPORT_DR_EPD1 (0x02) 98*4882a593Smuzhiyun #define EPORT_DR_EPD2 (0x04) 99*4882a593Smuzhiyun #define EPORT_DR_EPD3 (0x08) 100*4882a593Smuzhiyun #define EPORT_DR_EPD4 (0x10) 101*4882a593Smuzhiyun #define EPORT_DR_EPD5 (0x20) 102*4882a593Smuzhiyun #define EPORT_DR_EPD6 (0x40) 103*4882a593Smuzhiyun #define EPORT_DR_EPD7 (0x80) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* EPPDR */ 106*4882a593Smuzhiyun #define EPORT_PDR_EPPD1 (0x02) 107*4882a593Smuzhiyun #define EPORT_PDR_EPPD2 (0x04) 108*4882a593Smuzhiyun #define EPORT_PDR_EPPD3 (0x08) 109*4882a593Smuzhiyun #define EPORT_PDR_EPPD4 (0x10) 110*4882a593Smuzhiyun #define EPORT_PDR_EPPD5 (0x20) 111*4882a593Smuzhiyun #define EPORT_PDR_EPPD6 (0x40) 112*4882a593Smuzhiyun #define EPORT_PDR_EPPD7 (0x80) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* EPFR */ 115*4882a593Smuzhiyun #define EPORT_FR_EPF1 (0x02) 116*4882a593Smuzhiyun #define EPORT_FR_EPF2 (0x04) 117*4882a593Smuzhiyun #define EPORT_FR_EPF3 (0x08) 118*4882a593Smuzhiyun #define EPORT_FR_EPF4 (0x10) 119*4882a593Smuzhiyun #define EPORT_FR_EPF5 (0x20) 120*4882a593Smuzhiyun #define EPORT_FR_EPF6 (0x40) 121*4882a593Smuzhiyun #define EPORT_FR_EPF7 (0x80) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif /* __EPORT_H__ */ 124